• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• ETRI Journal
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• v.33 no.1
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• pp.71-77
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• 2011

Up to 10% of the global population suffers from color vision deficiency (CVD) [1], especially deuteranomaly and protanomaly, the conditions in which it is difficult to discriminate between red and green hues. For those who suffer from CVD, their career fields are restricted, and their childhood education is frustrating. There are many optical eye glasses on the market to compensate for this disability. However, although they are attractive due to their light weight, wearing these glasses will decrease visual brightness and cause problems at night. Therefore, this paper presents a supplementary device that comprises a head-mounted display and an image sensor. With the aid of the image processing technique of digital color space adjustment implemented in a high-speed field-programmable gate array device, the users can enjoy enhanced vision through the display without any decrease in brightness.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.561-562
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• 2011

인 휠 모터를 이용하여 구동되는 전기차량은 각 모터의 동기 제어가 요구된다. 기존의 마이크로컨트롤러는 구동시킬 수 있는 모터의 개수가 제한되어 인 휠 모터를 이용하여 구동되는 전기차량과 같은 다축 제어 시스템에 적용하기가 어렵다. 따라서 본 논문에서는 FPGA(Field Programmable Gate Array)를 이용하여 4축 동기 SVPWM 기법을 구현하였으며, 시뮬레이션을 통하여 성능을 확인하였다.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1682-1691
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• 2015

In this paper, a real time implementation of selective harmonic elimination pulse width modulation (SHEPWM) using Real Coded Genetic Algorithm (RGA), Particle Swarm Optimization technique (PSO) and a new technique known as Linearization Method (LM) for Single Phase Matrix Converter (SPMC) is designed and discussed. In the proposed technique, the switching frequency is fixed and the optimum switching angles are obtained using simple mathematical calculations. A MATLAB simulation was carried out, and FFT analysis of the simulated output voltage waveform confirms the effectiveness of the proposed method. An experimental setup was also developed, and the switching angles and firing pulses are generated using Field Programmable Gate Array (FPGA) processor. The proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real time applications.

• International Journal of Contents
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• v.11 no.4
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• pp.70-76
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• 2015

The development of technology provides and increases security as well as convenience for humans. The development of new technology directly affects the standard of life thanks to smart home automatic control systems. This paper describes a door control, automatic curtain, home security (CCTV, fire, gas, safe, etc.), home control (energy, light, ventilation, etc.) and web-based smart home automatic controller. It also describes the use of ARM (Advanced RISC Machines) for automatic control of home equipment, a Multi-Axes Servo Controller using FPGA (Field Programmable Gate Array) and PLC (programmable logic controller). Additionally, it describes the development of a HTML editor using web auto control software. The tab loading time (7 seconds) is faster when using ARM-based web browser software instead of Chrome and Firefox is used because the browser has a small memory footprint (300M). This system is realized by web auto controller language which controls and uses PLCs that are easier than existing devices. This smart home automatic control technology can control smart home equipment anywhere and anytime and provides a remote interface through mobile equipment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.437-438
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• 2018

본 논문은 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 프로그램 가능한 디지털 필터를 제안한다. 이러한 필터는 Altera사의 FPGA(Field Programmable Gate Array)인 cycloneII EP2C70F89618를 이용하여 구현하였다. 데이터 신호에 포함된 잡음 제거 알고리즘을 바탕으로 한 출력 영상 신호 결과로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 잡음이 제거된 출력 영상 특성을 보임을 확인하였다.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1139-1146
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• 2014

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.