• Title/Summary/Keyword: gate array

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High Performance Bottom Contact Organic TFTs on Plastic for Flexible AMLCD

  • Kim, Sung-Hwan;Choi, Hye-Young;Han, Seung-Hoon;Jang, Jin;Cho, Sang-Mi;Oh, Myung-Hwan
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.889-892
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    • 2004
  • We developed a high performance bottom contact, organic thin-film transistor (OTFT) array on plastic using a self-organized process. The effect of OTS treatment on the PVP gate insulator for the performance of OTFT on plastic has been studied The OTFT without OTS exhibited a field-effect mobility of 0.1 $cm^2$/Vs on/off current ratio of > $10^7$. On the other hand, OTFT with OTS, exhibited a field-effect mobility of 1.3 $cm^2$/Vs and on/off current ratio of>$10^8$.

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Display Panel for AMOLED with 64 x 64 Pixels on 2' Plastic Substrate

  • Song, Chung-Kun;Ryu, Gi-Seong;Choe, Ki-Beom
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.356-358
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    • 2004
  • In this paper we fabricated and succeeded to demonstrate a test panel for AMOLED on 2" glass and PET substrate. The test panel consisted of an array of 64 x 64 pixels in which OLEDs was driven by pentacene TFT. OTFTs were made of the inverted staggered structure and employed polyvinylphenol as the gate insulator and pentacene thin film as the active layer, producing the filed effect mobility of 0.3$cm^2$/V.sec and on/off current ratio of $10^5$. OLEDs were composed of TPD for HTL and Alq3 for EML with 35nm thick each, generating green monochrome light.

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A Implementation of PRT Current Control Algorithm for Current-Controlled Voltage Source Inverter (전류제어형 전압원 인버터용 PRT 전류제어알고리즘 구현)

  • Kwon, Hyuk-Dae;Park, Chun-Sung;Yoo, Won-Ho;Choi, Jae-Hyuk;Ko, Sung-Hun;Lee, Seong-Ryong
    • Proceedings of the KIEE Conference
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    • 2008.04c
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    • pp.146-148
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    • 2008
  • 본 논문에서는 계통의 전력품질을 향상시키기 위해 사용되어지는 전류제어형 전압원 인버터를 구동하기 위한 PRT(Polarized RamTime) 전류제어알고리즘의 구현방법을 설명한다. PRT 전류제어알고리즘은 스위칭 시퀀스의 예측이 가능하고 히스테리시스 전류제어기법의 단점인 가변스위칭 주파수 문제를 해결할 수 있다. 본 연구에서는 전류제어형 전압원인버터용 PRT 전류제어알고리즘을 FPGA(Field Programmable Gate Array)를 이용하여 구현하였고, 이의 유용성을 확인하기 위해 1KVA급 계통연계 전류제어형 전압원 인버터에 적용하여 실험 하였다.

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A digital frame phse aligner in SDH-based transmission system (SDH 동기식 전송시스템의 디지철 프레임 위상 정열기)

  • 이상훈;성영권
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.34S no.12
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    • pp.10-18
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    • 1997
  • The parallel trabutary signals in the SDH-based transmission system have the frame phase skew due to uneven transmission delays in the data and the clock path. This phase skew must be eliminated prior to synchronously multiplexing process. A new twenty-four channel, 51.84Mb/s DFPA(Digital Frame Phase Aligner) has been designed and fabricated in 0.8.mu.m CMOS gate array. This unique device phase-aligns the skewed input signals with refernce frame synchronous signal and reference clok for subsequent synchronous multiplexing process. the performance of fabricated device is evaluated by the STM-16 transmission system and DS-3 meansurement set. The frame phase margin of +2/-3 bit periods has been demonstrated.

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Color Image Enhancement Based on Adaptive Nonlinear Curves of Luminance Features

  • Cho, Hosang;Kim, Geun-Jun;Jang, Kyounghoon;Lee, Sungmok;Kang, Bongsoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.60-67
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    • 2015
  • This paper proposes an image-dependent color image enhancement method that uses adaptive luminance enhancement and color emphasis. It effectively enhances details of low-light regions while maintaining well-balanced luminance and color information. To compare the structure similarity and naturalness, we used the tone mapped image quality index (TMQI). The proposed method maintained better structure similarity in the enhanced image than did the space-variant luminance map (SVLM) method or the adaptive and integrated neighborhood dependent approach for nonlinear enhancement (AINDANE). The proposed method required the smallest computation time among the three algorithms. The proposed method can be easily implemented using the field-programmable gate array (FPGA), with low hardware resources and with better performance in terms of similarity.

Design of a G-Share Branch Predictor for EISC Processor

  • Kim, InSik;Jun, JaeYung;Na, Yeoul;Kim, Seon Wook
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.5
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    • pp.366-370
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    • 2015
  • This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

Development of a Fine Digital Sun Sensor for STSAT-2

  • Rhee, Sung-Ho;Lyou, Joon
    • International Journal of Aeronautical and Space Sciences
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    • v.13 no.2
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    • pp.260-265
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    • 2012
  • Satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2). Based on the mission requirements of STSAT-2, the conventional analog-type sun sensors were found to be inadequate, motivating the development of a compact, fast and fine digital sun sensor (FDSS). The FDSS uses a CMOS image sensor and has an accuracy of less than 0.03degrees, an update rate of 5Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize its weight. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA), which acquires images from the CMOS sensor, and stores and processes the image data. The sensor accuracy is maintained by a rigorous centroid algorithm. This paper describes the FDSS designs, realizations, tests and calibration results.

A SEC-DED Implementation Using FPGA for the Satellite System (위성체용 2비트 오류검출 및 1비트 정정 FPGA 구현)

  • No, Yeong-Hwan;Lee, Sang-Yong
    • Journal of Institute of Control, Robotics and Systems
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    • v.6 no.2
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    • pp.228-233
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    • 2000
  • It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

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FPGA based POS MPPT control for a small scale charging system of PV-nickel metal hydride battery (FPGA를 이용한 소형 태양광 발전 니켈 수소 전지 충전 시스템의 POS MPPT 제어)

  • Lee, Hyo-Geun;Seo, Hyo-Ryong;Kim, Gyeong-Hun;Park, Min-Won;Yu, In-Keun
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.1306-1307
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    • 2011
  • Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

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A Study on Place and Route of Time Driven Optimization in the FPGA (FPGA에서 시간구동 최적화의 배치.배선에 관한 연구)

  • Kim, Hyeonho;Lee, Yonghui;Cheonhee Yi
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04c
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    • pp.283-285
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    • 2003
  • We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

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