• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.186-189
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and room temperature process. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing process. The OTFT array with dielectric layer and organic active semiconductor layer formed at room temperature or at a temperature lower than $40^{\circ}C$. The microcontact printing process using SAM and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even submicron size, and reduced the fabrication process by 10 steps compared with photolithography. Since the process was done in room temperature, there was no pattern shrinkage, transformation, and bending problem appeared. Also, it was possible to improve electric field mobility, to decrease contact resistance, to increase close packing of molecules by SAM, and to reduce threshold voltage by using a big dielectric.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.595-596
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and low-temperature processes. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing which is high-resolution lithography technology using polydimethylsiloxane(PDMS) stamp. The OTFT array with dielectric layer and organic active semiconductor layers formed at room temperature or at a temperature tower than $40^{\circ}C$. The microcontact printing process using SAM(self-assembled monolayer) and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even nano size, and reduced the procedure by 10 steps compared with photolithography. Since the process was done in low temperature, there was no pattern transformation and bending problem appeared. It was possible to increase close packing of molecules by SAM, to improve electric field mobility, to decrease contact resistance, and to reduce threshold voltage by using a big dielecric.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1573-1576
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• 2004

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.157.6-157
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• 2001

We estimated various neuron functions to construct of engineering neurons, which are the combination of sigmoid, linear, sine, quadric, double/single bended, soft max/minimum functions. These combinations are estimated by the property on the potential surface between the learning points, calculation speed, and learning convergence; because the surface depends on the inference ability of a neuron system; and speed and convergence are depend on the efficiency on the points of engineering applications. After the evaluating discussions, we can select more appropriate combination than original sigmoid function´s, which is single bended function and linear one. The combination ...

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.84.5-84
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• 2002

In order to be a stand-alone structure, a biped robot should be designed of the effective mechanic structure and the smaller hardware system. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU and FPGA as the motor controller...

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1346-1349
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• 2002

This paper presents the design and implementation of 16-QAM modem that can be applied to fixed broadband wireless access systenm. It is implemented in the hardware prototype that consist of FPGA(Field Programmable Gate Array) for digital signal processing and analog front end module for analog signal processing. We provide 20.48Mbps data rate using implemented modem and test the modem in KOREA 26㎓ broadband wireless local loop system including IFU(Intermediate Frequency Unit) and RFU(Radio Frequency Unit) via air interface.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.97-100
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• 2001

A 3-way VLIW multimedia signal processor capable of efficient repeated operations as well as both load/store and type transformations for various data types is presented. It is composed of a 32-bit execution unit that can execute two instructions in parallel, an independent load/store unit and a control unit. The processor is implemented with 0.6${\mu}{\textrm}{m}$ gate array and the results are discussed.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.403-406
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• 2001

본 논문에서는 차세대 표준 알고리즘(AES: Advanced Encryption Standard)인 Rijndael 알고리즘의 고속화를 FPGA로 구현하였다. Rijndael 알고리즘은 미국 상무부 기술 표준국(NIST)에 의해 2000년 10월에 차세대 표준으로 선정된 블록 암호 알고리즘이다. FPGA(Field Programmable Gate Array)는 아키텍쳐의 유연성이 가장 큰 장점이며, 근래에는 성능면에서도 ASIC에 비견될 정도로 향상되었다. 본 논문에서는 128비트 키 길이와 블록 길이를 가지는 암호화(Encryption)블럭을 Xilinx VirtexE XCV812E-8-BG560 FPGA에 구현하였으며 약 15Gbits/sec의 성능(throughput)을 가진다. 이는 현재까지 발표된 FPGA Rijndael 알고리즘의 구현 사례 중 가장 빠른 방법 중의 하나이다.