• The Journal of the Korea Contents Association
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• 제20권1호
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• pp.593-604
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• 2020

The purpose of this study is to analyze parental gatekeeping dimensions(control, encouragement, discouragement) and types of gatekeeping in the two families featured in the drama 「SKY Castle」. Of the 8 types of gatekeeping, the traditional gate blocker(high control, low encouragement, and high discouragement) most often described in the drama, creates a difficult situation for a father trying to participate in child rearing. But traditional gate blockers do not always unnecessarily limit father involvement. In father's coerecive and dictatorial environment, traditional maternal gatekeeping strategies protect her children and create secure environment. The facilitative gate openers(high control, high encouragement, and low discouragement) is the functional gatekeeping type. Because the mother's highly controlling and highly encouraging ways serve as a positive coparenting strategy, the facilitative gate maintain a high level of authority over the amount and type of father involvement.

• Proceedings of the SCSK Conference
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• 대한화장품학회 2004년도 대한화장품학회/한국공업화학회 2004년 추계 공동심포지움
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• pp.1-8
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• 2004

고령화사회(aging society)에서 매우 빠른 속도로 고령사회(aged society)에 다가가고 있는 우리나라는 노인에 대한 개념을 새롭게 재정비하고 장수고령사회에 대비한 새로운 문화를 창출하여야 할 때이다. 노화란 개념에 대해서도 불가피하고 비가역적인 생체의 변화를 통한 죽음에 이르는 도정이라는 결정론적 시각을 불식하고, 노화현상은 생명체의 생존을 위한 적응적 반응성 변화라는 사실을 분명하게 하고, 그러한 변화의 요인이 제어가 가능한 생체의 변화임을 인식하여 노화 및 노인 문제에 대하여 새롭게 대처하여야 할 필요가 대두되고 있다. 아울러 노화현상에 대한 새로운 가설인 노화대문설(Gate theory of aging)의 기본을 설명하고 이를 바탕으로 한 기능적 장수(functional longevity)의 개념을 정리해본다.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제22권11호
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권1호
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• pp.206-221
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• 1995

Metal-Metal Matrix(M$^{3}$) layout is a recently proposed layout style which uses minimum amount of poly wires for high speed operation. In this paper we propose a method of generating functional modules in M$^{3}$ layout style. In the proposed method the transistors and the input/output lines of the given circuit are first placed in M$^{3}$ layout style and then they are interconnected using two metal layers. We develop a new placement method by simulated annealing, and we modify the well known channel routing method for the interconnections. When we applied our method to several logic circuits, the area of the generated layout is smaller than the ones by the previously known method. Our results also compares favorably to the other layout styles like gate matrix layout.

• The Magazine of the IEIE
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• 제30권9호
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• The Transactions of the Korea Information Processing Society
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• 제2권4호
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• pp.603-610
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• 1995

In this paper, we present a highly efficient simulation package which supports simulation from functional level to gate level. The package consists of a set of front-end tools, a logic simulator, named HSIM(Highly efficient logic SIMulator), and an waveform analyzer. The front-end tools include a netlist compiler, functional primitive compiler and behavioral compiler. Key feature of developed simulator is that the compiled behavioral models written in C language are directly executed in the simulation engine using incremental loader. By doing so, we achieved significant speed up as compared with the interpretive functional simulator. Experimental results show that HSIM runs about 55% faster than traditional unit-delay event-driven interpretive simulator.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• The Journal of the Korea Contents Association
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• 제9권9호
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• pp.151-162
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• 2009

As the aging population has increased, the silver generation is getting to account for the considerable percent of economic activities and becomes the main body of production and consumption. Although the economic activity of silver generation is increased, the development of silver contents for the leisure activities is still not revitalized. The serious silver contents and the easy-to-use interface are very important because the silver generation is relatively weaker than young people in perception, studying, and exercise, and is fragile in mobility and vitality. This paper suggests methods to develop sensory bicycle, gate ball, and mole game contents haying lower body exercise effects for the silver generation to utilize leisure and maintain health. Along with fun as games, functional design factors suitable to the cognitive ability and bodily activity ability of the silver generation were considered and through sensory intefaces that are easy for the silver generation to use and customized progressing methods complying with individual characteristics, it was attempted to induce continued interests and lower body exercise effects.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제22권10호
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• Proceedings of the KSR Conference
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• 한국철도학회 2009년도 춘계학술대회 논문집
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• pp.247-250
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• 2009

Awareness of resource conservation and pollution prevention has been continually increasing. The proven benefits from CFRP's unique combination of light weight and high strength compare to conventional material is well suited for minimizing fuel consumption during vehicle in particular rail operation. Responding the awareness, this work intends to study CFRP's recycling method that is not only technical performance but also environmental view point. According to prior work of technical performance test, this work aims at quantifying the footprint of energy and GHG derived from the two appreciated performance of pyrolysis and acids recycling methods. The streamline LCA is the concept for systematic assessment. The boundary is scoped at the recycling activity, consequently, the data in and out from the specific target activity are obtained under the gate to gate data collection. Its function is recovery carbon fiber. To count and compare function, functional unit is set at 60% of recycling rate. Korea database is mainly source for acquiring the footprint of both. The numerical results presented that the energy footprint of acids and pyrolysis is 164.95 and 1,199.88 MJ-eq., respectively. Meantime, the GHG footprint of is 1,196.22 and 5,916.08 g CO2 eq. for acids and pyrolysis. In summary, the acids recycling method is, in regarding the environmental performance, better than pyrolysis recycling method.