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Bandwidth-efficient Cooperative Diversity with Rotated Constellations and Its Performance Analysis

  • Lei, Weijia;Xie, Xianzhong;Li, Xiangming
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.6
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    • pp.989-1005
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    • 2010
  • Cooperative diversity is a technique with which a virtual multiple antenna array is established among the single antenna users of the wireless network to realize space diversity. Signal space diversity (SSD) is a bandwidth-efficient diversity technique, which uses constellation rotation and interleaving techniques to achieve diversity gain. A new cooperative diversity scheme with rotated constellations (RCCD) is proposed in this paper. In this scheme, data are modulated by using a rotated constellation, and the source and the relays transmit different components of the modulated symbols. Since any one of the components contains full information of the symbols, the destination can obtain multiple signals conveying the same information from different users. In this way, space diversity is achieved. The RCCD scheme inherits the advantage of SSD - being bandwidth-efficient but without the delay problem of SSD brought by interleaving. The symbol error rate of the RCCD scheme is analyzed and simulated. The analysis and simulation results show that the RCCD scheme can achieve full diversity order of two when the inter-user channel is good enough, and, with the same bandwidth efficiency, has a better performance than amplify-and-forward and detect-and-forward methods.

Calculation of Leakage Inductance of Integrated Magnetic Transformer with Separated Secondary Winding Used in ZVS PSFB Converter

  • Tian, Jiashen;Zhang, Yiming;Ren, Xiguo;Wang, Xuhong;Tao, Haijun
    • Journal of Magnetics
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    • v.21 no.4
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    • pp.644-651
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    • 2016
  • A novel zero voltage switching (ZVS) phase shift full bridge (PSFB) converter used in geophysical exploration is proposed in this paper. To extend the ZVS ranges and increase power density of the converter, external inductor acting as leakage inductance is applied and integrated into the integrated magnetic (IM) transformer with separated secondary winding. Moreover, the loss of ZVS PSFB converter is also decreased. Besides, the analysis and accurate prediction methodology of the leakage inductance of the IM transformer are proposed, which are based on magnetic energy and Lebedev. Finally, to verify the accuracy of analysis and methodology, the experimental and finite element analysis (FEA) results of IM transformer and 40 kW converter prototypes are given.

A Novel Social Aware Reverse Relay Selection Scheme for Underlaying Multi- Hop D2D Communications

  • Liang Li;Xinjie Yang;Yuanjie Zheng;Jiazhi Yang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.17 no.10
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    • pp.2732-2749
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    • 2023
  • Device-to-Device (D2D) communication has received increasing attention and been studied extensively thanks to its advantages in improving spectral efficiency and energy efficiency of cellular networks. This paper proposes a novel relay selection algorithm for multi-hop full-duplex D2D communications underlaying cellular networks. By selecting the relay of each hop in a reverse manner, the proposed algorithm reduces the heavy signaling overhead that traditional relay selection algorithms introduce. In addition, the social domain information of mobile terminals is taken into consideration and its influence on the performance of D2D communications studied, which is found significant enough not to be overlooked. Moreover, simulations show that the proposed algorithm, in absence of social relationship information, improves data throughput by around 70% and 7% and energy efficiency by 64% and 6%, compared with two benchmark algorithms, when D2D distance is 260 meters. In a more practical implementation considering social relationship information, although the proposed algorithm naturally achieves less throughput, it substantially increases the energy efficiency than the benchmarks.

Optimization Using 33 Full-Factorial Design for Crude Biosurfactant Activity from Bacillus pumilus IJ-1 in Submerged Fermentation

  • Kim, Byung Soo;Kim, Ji Yeon
    • Microbiology and Biotechnology Letters
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    • v.48 no.1
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    • pp.48-56
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    • 2020
  • This study aimed to optimize the culture conditions to improve the crude biosurfactant activity of Bacillus pumilus IJ-1, using a 33 full-factorial design of response surface methodology (RSM). It was found that submerged fermentation of B. pumilus improved the activity of the crude biosurfactant. The factors selected for optimization were NaCl concentration, temperature, and tryptone concentration. Response surface analysis revealed that the fitted quadratic model was statistically significant and produced an adequate R2 value (0.9898) and a low probability value (<0.0001). The optimum level for each factor was found to be 0.567% (w/v) NaCl, 21.851℃ and 0.765% (w/v) tryptone, respectively. Crude biosurfactant activity was found to be most affected by tryptone concentration; then temperature, and finally NaCl concentration. Our results may potentially facilitate large-scale biosurfactant production from B. pumilus IJ-1.

A Full Rate Dual Relay Cooperative Approach for Wireless Systems

  • Hassan, Syed Ali;Li, Geoffrey Ye;Wang, Peter Shu Shaw;Green, Marilynn Wylie
    • Journal of Communications and Networks
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    • v.12 no.5
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    • pp.442-448
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    • 2010
  • Cooperative relaying methods have attracted a lot of interest in the past few years. A conventional cooperative relaying scheme has a source, a destination, and a single relay. This cooperative scheme can support one symbol transmission per time slot, and is caned full rate transmission. However, existing fun rate cooperative relay approaches provide asymmetrical gain for different transmitted symbols. In this paper, we propose a cooperative relaying scheme that is assisted with dual relays and provides full transmission rate with the same macro-diversity to each symbol. We also address equalization for the dual relay transmission system in addition to addressing the issues concerning the improvement of system performance in terms of optimal power allocations.

System Identification of a Full Scale Five-story building for Vibration Controller design (진동제어기 설계를 위한 실물크기 5층 건물의 시스템 식별)

  • Min, Kyung-Won;Lee, Young-Cheol;Lee, Sang-Hyun;Park, Min-Kyu;Kim, Doo-Hoon;Park, Jin-Il;Jeong, Jeoung-Kyo
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.11b
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    • pp.676-681
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    • 2002
  • System Identification is carried out for a full scale five-story builing to design a vibration controller. Dynamic characteristics such as natural frequencies, damping ratios, and modes are obtained from the input/output information by both sine-sweep method and white noise method. The active mass driver installed on the five floor is applied as external loading to move the building and each floor acceleration is measured and processed for the system identification. The identified building will be experimentally investigated again with viscoelastic dampers installed at inter-stories to obtain the response behavior. Corresponding result will be presented soon.

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Deployment of KT Broadband network based on FS-VDSL Specification (FS-VDSL 표준을 이용한 KT 브로드밴드 망구축)

  • Kim Hong-Seok;Park Hyung-Jin;Yoo Gun-Il
    • 한국정보통신설비학회:학술대회논문집
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    • 2002.08a
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    • pp.110-113
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    • 2002
  • FS-VDSL은 B-PON과 VDSL을 이용하여 가입자에게 디지털TV, VOD, 초고속인터넷, 전화 등을 총 망라한 Full Service를 제공하기 위해 필요한 모든 망구조 및 프로토콜에 대해서 규정한다. FS-VDSL의 전신은 FSAN xDSL working group이며, FSAN에서 정의한 B-PON을 기본적인 액세스망으로 정의하고 있다. 본 논문에서는 End-to-end Full Service 제공을 위하여 FS-VDSL에서 솔루션으로 제시하고 있는 하이브리드 코어망, B-PON 및 VDSL 액세스망, Ethernet 홈네트워크를 포함하는 End-to-end 망구조 및 각각의 프로토콜에 대하여 살펴본다. 또한 Full Service의 핵심인 영상서비스 수용을 위하여 효율적인 비디오 트래픽 전달이 가능한 비디오 인켑슐레이션 프로토콜 및 DBTV 채널변경 프로토콜 등에 대하여 살펴보고, FS-VDSL에서 제시하는 방안을 이용한 KT의 브로드밴드 망구축 적용성에 대해 살펴본다.

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Asymmetrical Pulse-Width-Modulated Full-Bridge Secondary Dual Resonance DC-DC Converter

  • Chen, Zhangyong;Zhou, Qun;Xu, Jianping;Zhou, Xiang
    • Journal of Power Electronics
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    • v.14 no.6
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    • pp.1224-1232
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    • 2014
  • A full-bridge secondary dual-resonant DC-DC converter using the asymmetrical pulse-width modulated (APWM) strategy is proposed in this paper. The proposed converter achieves zero-voltage switching for the power switches and zero-current switching for the rectifier diodes in the whole load range without the help of any auxiliary circuit. Given the use of the APWM strategy, a circulating current that exists in a traditional phase-shift full-bridge converter is eliminated. The voltage stress of secondary rectifier diodes in the proposed converter is also clamped to the output voltage. Thus, the existing voltage oscillation of diodes in traditional PSFB converters is eliminated. This paper presents the circuit configuration of the proposed converter and analyzes its operating principle. Experimental results of a 1 kW 385 V/48 V prototype are presented to verify the analysis results of the proposed converter.

Efficient Control Method for ZVS Full-Bridge Converter with Periodic Pulsed-Load Output Dynamic Improvement (주기적인 펄스 부하에서 ZVS Full-Bridge 컨버터의 효율 증대를 위한 제어 방법과 출력 동특성 향상 분석)

  • Lee, Dong-Young;Kim, Jung-Won;Cho, Bo-Hyung
    • Proceedings of the KIEE Conference
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    • 2001.07b
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    • pp.939-941
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    • 2001
  • An efficient control method of ZVS Full-bridge PWM converter with a periodic pulsed-load current is proposed. This novel control method can reduce the switching loss of switches during no load condition. Moreover, by using feed-forwarded load current information this method can obtain better transient dynamics compared to the system with only linear feedback control.

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A real-time high speed full search block matching motion estimation processor (고속 실시간 처리 full search block matching 움직임 추정 프로세서)

  • 유재희;김준호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.12
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    • pp.110-119
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    • 1996
  • A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

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