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Design and implementation of dual-mode narrow-band waveguide channel filter using measured iris transmission loss data (Iris 전송손실 측정값을 이용한 이중모드 협대역 도파관 채널여파기의 설계 및 제작)

  • 정근욱;이재현
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.6
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    • pp.19-28
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    • 1995
  • In this paper, measured iris transmission loss data and simulated data by using 3-dimension full-wave analysis S/W are presented and compared with Marcuvitz's theory. And by using measured iris data, dual-mode narrow-band channel filters can be successfully implemented. This paper shows that there is severe difference between the transmission loss of iris calculated by using Marcuvitz's equation to calculate iris dimension, if the length of slot iris is longer than .lambda./.pi., and in the long urn the response of channel filter is distorted. Experimental result shows that the characteristic response of implemented channel filter by using the iris transmission loss graph presented here matches well the design specfications. In conclusion, iris transmission loss measurement method will be very useful to design channel filter.

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Measurement of Relative Position between Spreader and Target Container with Image Processing (Proposal for Composition of New Template Image)

  • Munimitsu, Satoshi;Asama, Hajime;Kawabata, Kuniaki;Mishima, Taketoshi
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.1224-1227
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    • 2002
  • In this paper, we propose a composition method of the template image whose detection performance does not have incorrect detection and improves also on the tough photography conditions of the outdoors, rainy weather and night. This research was done to measure a relative position between a spreader and a target container with image processing to realize full-automatic quayside gantry cranes. By the proposal method, we confirmed that the template image for object detection has a contour image more effective than a gray image.

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VLSI Implementation of High Speed Variable-Length RSA Crytosystem (가변길이 고속 RSA 암호시스템의 VLSI 구현)

  • 박진영;서영호;김동욱
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.285-288
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    • 2002
  • In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.

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Component-Based VHDL Analyzer for Reuse and Embedment (재사용 및 내장 가능한 구성요소 기반 VHDL 분석기)

  • 박상헌;손영석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1015-1018
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    • 2003
  • As increasing the size and complexity of hard-ware and software system, more efficient design methodology has been developed. Especially design-reuse technique enables fast system development via integrating existing hardware and software. For this technique available hardware/software should be prepared as component-based parts, adaptable to various systems. This paper introduces a component-based VHDL analyzer allowing to be embedded in other applications, such as simulator, synthesis tool, or smart editor. VHDL analyzer parses VHDL description input, and performs lexical, syntactic, semantic checking, and finally generates intermediate-form data as the result. VHDL has full-features of object-oriented language such as data abstraction, inheritance, and polymorphism. To support these features special analysis algorithm and intermediate form is required. This paper summarizes practical issues on implementing high-performance/quality VHDL analyzer and provides its solution that is based on the intensive experience of VHDL analyzer development.

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Cost-effective multistage interconnection network for UNMA model system (NUMA(non-uniform memory access) 모델 시스템을 위한 cost-effective한 다단계 상호연결망)

  • 최창훈;김성천
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.5
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    • pp.19-32
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    • 1997
  • So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

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A Study on the Implementation of Format Converter using Median Filter (메디안 필터를 이용한 포맷 변환기 구현에 관한 연구)

  • 김현기;하기종;최영규;류기한;이천희
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1137-1140
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    • 2003
  • The area of the prototype device is less than 80mm$^2$. Operating with a 60ns clock cycle, the device typically dissipates only 300mW. The full functionality was proven by using the methodical test programs based on typical image processing operations. Also, we realized the whole process from conventional gray image to color image. Format converters, implemented using multidimensional access memories, transfer the data between the processing element array and conventional bit-parallel components in real time. The completed system is fully functional and performs typical low-level image processing tasks at speed exceeding 30 frames of traditional TV system per second.

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Current Controlled Negative Resistance Circuit Using JFET and Bipolar Transistor (JFET와 트랜지스터를 이용한 전류제어부저항회로)

  • 최시영
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.14 no.5
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    • pp.29-34
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    • 1977
  • Using JFET and bipolar transistor, we have designed a circuit of current controlled negative resitance and analysed this circuit in the operating region. Since the positive gate voltage of N-channel JFET is applied in full operating region, the output and transfer characteristics of JFET are measured in the positive gate region. The performances of this circuit are predicted from these characteristics and experimental results of the proposed CCNR circuit are presented.

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Construction of Web-Based EDMS Supporting Full-Text Information System (웹 환경의 EDMS를 위한 전문 정보시스템 구축)

  • Kim, S.D.;Kim, G,H.;Lee, Y.C.
    • Electronics and Telecommunications Trends
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    • v.13 no.6 s.54
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    • pp.124-136
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    • 1998
  • 본 연구는 최근 들어 각광을 받고 있는 전자문서관리시스템(EDMS)의 주요 기능 중에서 문서의 공유와 문서 형식(file format)의 변환을 통한 전자문서 관리의 효용성 향상을 위해서 어떻게 전문 정보를 구축할 것인가에 초점을 맞추고 문서의 통합 기능을 제공하는 웹 기반의 EDMS를 설계 및 구현하였다. 이를 위하여 인터넷상에서 현재 표준 문서형식으로 사용 중이거나 개발중인 전자문서 포맷들의 특징을 비교, 분석하고, 정보 시스템의 관점에서 전문정보를 어떤 문서 포맷으로 처리하는 것이 적합한가를 검토하였다. 그리고 기존의 문헌을 전자화 하고 새로운 전자문헌을 제작하기 위한 보다 효율적인 방안 제시를 위하여 전문(全文) 정보를 PDF 문서로 제공하는 정보 시스템을 구현하였다.

An Onsite Test by Full-Test Procedures of ISO GNSS RTK Standard (GNSS RTK 표준규격의 엄밀시험절차에 따른 현장시험)

  • Lee, Young-Jin;Jo, Jun-Rae;Song, Jun-Ho;Jung, Rae-Jung
    • Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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    • 2009.04a
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    • pp.293-294
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    • 2009
  • 정밀한 관측을 요하는 측량장비의 기능을 보정하거나 검증하는 것은 측량시 매우 중요한 일이다. ISO17123-8 규격은 GNSS RTK 정확도를 결정 할 때 사용되는 야외실험 절차와 규정을 명시하고 있으며 정확도 평가방법으로는 약식시험절차와 엄밀시험절차를 제시하고 있다. 본 연구에서는 GNSS RTK 정확도 평가방법 중 엄밀시험절차에 대해 시험할 목적으로 GNSS RTK 규격에 따라 Test-bed를 구축하였고 성능실험을 실시 위하여 GNSS RTK 규격에 제시된 정확도 평가방법을 적용하였다.

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EXPERIMENTAL STUDY ON THE HEAVY-DUTY GAS TURBINE COMBUSTOR (산업용 가스터빈 연소기에 대한 실험적 연구)

  • Antonovsky, V.;Ahn, Kook-Young
    • Proceedings of the KSME Conference
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    • 2000.11b
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    • pp.142-149
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    • 2000
  • The results of stand and field testing of a combustion chamber for a heavy-duty 150 MW gas turbine are discussed. The model represented one of 14 identical segments of a tubular multican combustor constructed in the scale 1:1. The model experiments were executed at a pressure smaller than in the real gas turbine. The combustion efficiency, pressure loss factor, pattern factor, liner wall temperature, flame radiation, fluctuating pressure, and NOx emission were measured at partial and full load for both model and on-site testing. The comparison of these items of information, received on similar modes in the stand and field tests, has allowed the development of a method of calculation and the improvement of gas turbine combustors.

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