• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.276-284
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• 2013

This paper considers the transfer alignment in the inertial navigation system and the observability analysis is performed for velocity matching. The state variable of the Kalman filter is modeled including the lever arm error and the measurement equation is obtained. The SOM(Stripped Observability Matrix) method is used for the observability analysis for various maneuvering conditions of the vehicle, which gives the full state observability condition as a specific maneuver sequence of the vehicle. While the observability analysis of a lever arm effect in the existing papers is mainly performed by simulations, we performed it analytically by the observability analysis method. The analysis result is verified using the computer simulations.

• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.141-146
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• 1999

In this paper, picture set filter is proposed for preserving compression ratio and video qualify. This filter controls the compression ratio of each frame depending on the correlation to the reference frame by selectively eliminating less important high-resolution areas. Consequently, video quality can be preserved and bit rate can be controlled adaptively. In the simulation, to test the performance of the proposed coding method, comparisons with the full search block matching algorithm and the differential image coding algorithm are made. In the former case, video quality, compression ratio and encoding time is improved. In the latter case, video quality is degraded, but compression ratio and encoding time is improved. Consequently. the proposed method shows a reasonably good performance over existing ones.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.40-45
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• 2002

There has been several meaning full efforts to save costs and expand the life-time of a system in changeful If circumstance. It was a module-based architecture that empower productivity at structured programming. It couldn't grow nor evolve, but could raise only calling frequency of module. But OOP or OO-method overcome limit of structured programing by class inheritance and/or overloading and/or over-riding. A component centric architecture, what is mixture of distributed systems, like CORBA. COM+ or EJB/J2EE with OOP. can support not only high reusability or expansion of life-time but also Plug-&-Play between component. In now day. It is not problem of component building but problem of interoperability between heterogeneous CBD Platform. At this study, the enhanced referential component architecture will be suggested.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.3
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• pp.1279-1300
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• 2017

In the interweave cognitive networks, the interference from the primary user degrades the performance of the cognitive user transmissions. In this paper, we propose an adaptive cooperation scheme in the interweave cognitive networks to improve the performance of the cognitive user transmissions. In the proposed scheme for the bidirectional communication of two end-source cognitive users, the bidirectional communication is completed through the non-relay direct transmission, the one-way relaying cooperation transmission, and the two-way relaying cooperation transmission depending on the limited feedback from the end-sources. For the performance analysis of the proposed scheme, we derive the outage probability and the finite-SNR diversity multiplexing tradeoff (f-DMT) in a closed form, considering the imperfect spectrum sensing, the interference from the primary user, and the power allocation between the relay and the end-sources. The results show that compared with the direct transmissions (DT), the pure one-way relaying transmissions (POWRT), and the pure two-way relaying transmissions (PTWRT), the proposed scheme has better outage performance. In terms of the f-DMT, the proposed scheme outperforms the full cooperation transmissions of the POWRT and PTWRT.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1537-1545
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• 1993

In this paper, we design a pattern generator and a fault position detector to implement the proposed fault test algorithms which are Column Weight Sensitive Fault (CWSF) test algorithm and bit line decoder fault test algorithm for performing the Built-In Self Test(BIST) in RAM. A pattern generator consists of an address generator and a data generator. An address generator is divided into a row address generator for effective address and a column address generator for sequential and parallel addresses. A fault position detector is designed to determine whether full occurred or not and to find the position of the fault. We verify the implemented circuits by the simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.685-690
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• 1994

A problem associated with vector quantization(VQ) is the computational complexity incurred in searching for a codevector with the closet to a given input vector, where the complexity increases exponentionally with proportion to codebook size and then limits practical application. In this paper, a simple and fast, but efficient, VQ encoding algorithm is presented using a reference codevector as start codevector of premature exit condition, which eliminates distance claculation of unlikely codevectors. The algorithm is to find reference codevector having the possibility to be the nearest vector to input vector first and then to incorporate premature exit condition. The proposed algorithm needs only 10~15% of mathematical operations compared with the conventional full search VQ. Algorithm the number of additions and comparsions of the proposed algorithm is not reduced greatly, the number of multiplication is reduced up to 70~80% compared with other fast VQ encoding methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.484-488
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• 2000

This paper proposes a highy efficient inverter circuit for fluorescent lamp inverters using two state capacitors. A waveform of full-wave rectification used as a direct current power supply at fluorescent lamp inverters contains a lot of harmonic wave from inrush current which is generated near the maximum of input voltage with purse shape when voltage smoothing capacitor is charged. Therefore, In order to suppress inrush current which will result in harmonic wave, This paper proposed a method to control abrupt charging current by use of charging voltage at pre-state capacitor. As the result of it, power factor comes to be improved through the suppression of harmonic wave generation at supply current. Validity as to this experiment is confirmed through simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1291-1296
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• 2003

This paper deals with efficient diagnostic for stator winding fault of 3-phase induction motor using a current Park's vector approach. This method firstly transforms 3-phase stator current to vertical axis current and horizontal axis current of Park's Vector, and then obtains the each Park's Vector Pattern and detects stator winding fault by comparing to Park's Vector Pattern of healthy and fault. Experimental results, obtained by using induction motor having inter-turn fault of 2, 10, 20 turn, demonstrate the effectiveness of the proposed technique, for detecting the presence of stator winding fault under 25%, 50%, and 100% of full load condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.294-299
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• 2002

This paper presents a faults diagnosis technique of induction motors based on a neural network. Only stator current is measured, transformed by using FFT and normalized for the training. Healthy, bearing fault, stator fault and rotor end-ring fault motors are prepared to obtain the learning data and diagnose the several faults. For more effective diagnosis, the load rate is changed by 100%, 60%, 30% of full load and the obtained are applied to the teaming process. The experimental results show the proposed method is very detectable and applicable to the real diagnosis system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1283-1291
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• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.