• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• International Commerce and Information Review
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• v.6 no.3
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• pp.203-224
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• 2004

The purpose of this study is to review and analyze the protection measures for the importer's interests through the utilization of electronic delivery order(e-D/O) with the implementation of trade facilitation measures such as the simplification of customs procedures by the Korea Customs Service. The Korea Customs Service has been introducing several custom facilitation measures through the use of EDI system in the export and import processes. Korea has also already achieved a comparable level of sophistication in trade automation and custom simplification field. However, the full benefits of the trade automation and custom simplification measures have not yet achieved through the frequent illegal delivery of the imported goods in the bonded areas. Therefore, it is argued in this study that the introduction and the full utilization of e-D/O would help to reap the trade automation and custom simplification measures in Korea. In conclusion, it is emphasized that it would be very crucial for the Korean government to introduce the trusted repository for distribution of the electronic trade-related documents and the construction of the one stop single window platform for the trade and customs facilitation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.798-804
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• 2003

In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.362-368
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• 2001

본 논문에서는 두 개의 17비트 오퍼랜드를 radix-4 Booths 알고리즘을 이용하여 곱셈 연산을 수행하는 곱셈기를 설계하고 효율적인 풀커스팀 디자인에 대한 테스트 방법을 제안하였다. 클럭 속도를 빠르게 하기 위하여 2단파이프라인 구조로 설계하고 규칙적인 레이아웃을 위해 4:2 CSA(Carry Save Adder)를 사용하였다. 회로는 LG 반도체의 0.6-um 3-Metal N-well CMOS 공정을 사용하여 칩으로 제작되었다. 새로운 개념의 모듈레벨 고착 고장 모델을 제안하였고 제안한 테스트 방법을 사용하여 관찰해야 하는 노드의 수를 약 88% 줄여 효율적인 고장 시뮬레이션을 수행하였다. 설계된 곱셈기는 9115개의 트랜지스터로 구성되며 코어 부분의 레이아웃 면적은 약 1135*1545 um2 이다. 제작된 칩은 전원접압 5V에서 약 24MHz의 클럭 주파수로 동작한다.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.517-530
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• 1994

In this paper, design of small microprocessor unit is implemented using research purpose VHDL and CAD tools by top-down design method. For this, original basic MPU and its pipelining architectures are suggested. Once, design target, instruction sets, architecture are decided, the operation is confirmed by C language simulation, and then the operation is confirmed by checking internal register contents for given inputs in the case of VHDL simulation. Then, design layouts are made by full/semi-custom design methods by research CAD tools and related simulation is implemented. The feasibility of suggested pipelined structure for performance improvement is confirmed by simulation, and related problems and future research directions are discussed. In conclusion, the MPU design methodology is set up and the design change of architecture is possible by this paper.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.6
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• pp.729-734
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• 2011

The full sintering process of zirconia has some extent of shrinkage and the custom abutment design should consider the pre-compensation volume of the shape. In this paper, we concentrated to reveal the asymmetric sintering characteristics. The circular profile of all six samples were measured using the three dimensional coordinate machine. After the full sintering process, the profiles were measured again. The roundness were compared to those of the original shapes and the percent of shrinkage were calculated. On the other hand, surface roughness was also investigated after the full sintering process. The final average surface roughness was improved by the sintering of the machined zirconia surface.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.1-6
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• 1997

This paper describes the design of a network interface controller (NIC) chip which is to be used to support a novel adaptive virtual cut-through routing method for parallel compute systems with direct (i.e., point-to-point) interconnection networks. The NIC chip is designed to provide the interface between a processing node constructed from commercially available microprocessors and another custom-designed router chip, which in turn performs the actual routing of packets to their respective destinations. The NIC, designed using a semi-full-custom VLSi design technique outperform traditional wormhole routing with a minimal amount of hardware overhead. The NIC design has been fully simulated and laid out using a 0.8$\mu\textrm{m}$ CMOS process.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.974-979
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• 1990

The system discussed in this paper is an integrated stand-alone system with the full functional capabilities required of a telerobot system. It is complete with a force-reflecting 6-DOF hand controller, driving a PUMA 560 or 762 robot, with an integrated force-torque sensing wrist sensor and servo-driven parallel jaw gripper. A mix of custom and standard electronics, distributed computers and microprocessors, with embedded and downloadable software, have been integrated into the system, giving rise to a powerful and flexible teleautonomous control system.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.951-954
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• 1999

A direct digital frequency synthesizer is designed in full custom method using 0.65${\mu}{\textrm}{m}$ CMOS n-well technology The chip provides the capability of the parallel operation using up to 4 chips with an operation frequency of 440MHz. The generated waveform can be modulated by various modulation techniques such as QPSK, 256 . 64. 32 . 16 QAM and FM.