• 한국산업정보학회논문지
• /
• 제18권5호
• /
• pp.15-18
• /
• 2013

본 논문은 뇌전도 신호 처리를 위한 아날로그 전단부를 제시한다. 일반적으로 뇌전도 신호는 낮은 주파수 대역에 존재하고 신호의 크기가 미약하므로 이를 처리하기 위한 아날로그 전단부는 높은 전압 이득 및 공통모드 제거비를 가져야 하며 저주파 잡음을 효과적으로 억제해야 한다. 본 논문에서 제시하는 아날로그 전단부는 가변 이득 계측 증폭기와 대역통과 필터로 구성되어 있다. 낮은 주파수의 잡음을 제거하기 위하여 주파수 chopping을 적용하였다. 본 논문의 회로는 0.18um CMOS 공정을 이용하여 제작하였으며 측정 결과 최대 60dB의 전압이득과 100dB 이상의 공통모드 제거비를 내는 것을 확인하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.155-158
• /
• 2005

An invesitigation on power consumption of a mobile multimedia system using OFDM and MDVS technique is reported here. Analysis and simulation are performed to find the significances of proposed Microscopic Dynamic Voltage Scaling(MDVS) tehnique[4] on digital processor in terms of power saving. A study is also made to show power reduction in mobile multimedia system by incorporating OFDM modulation scheme in RF front-end. Finally, overall power consumption by functionally distinguished blocks ie. RF front-end, digital processor and human interface unit is shown here. Total power consumption is 8.2W for 2Mbps SD-quality WCDMA multimedia video service - the power consumption of digital processor is 3.9W(48%), the power consumption of RF front-end is 3.2W (36%), and the power consumption of interface is 1.8W(16%). Power saving of applying purposed MDVS technique is 35% in digital processor, and power saving of OFDM technique is 10-12dB in RF front-end.

• 대한의용생체공학회:의공학회지
• /
• 제7권1호
• /
• pp.59-66
• /
• 1986

개발된 초음파 섹터 B-스캐너 시제품에서 프론트 엔드 하드웨어는 초음파펄스의 송신 및 수신을 담당하는 부분으로서 변환자에 펄스를 인가하는 펄스발생기, 진폭이 미약한 애널로그 신호를 처리하는 수신회로 및 기계식 섹터 탐촉자를 구동하는 조향제어회로의 3부분으로 크게 나눌 수 있다. 본 논문에서는 위 3부분의 기능 및 설계에 관하여 기술한다. 완성된 프론트 엔드 하드웨어의 특징 가운데 중요한 몇가지만 살펴보면, 링다운 시간을 감소시키는 펄스발생기를 사용하여 축방향의 해상도를 증가시켰고 시가변이득 증폭기에 필요한 제어전압을 여러 형태로 만들 수 있으며 탐촉자내에 있는 감지기의 출력파형을 기준으로 본 초음파 진단장치의 모든 시스템에 공급될 레이트 펄스를 만들어 주는 것이라고 말할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제9권2호
• /
• pp.85-90
• /
• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• 한국정보통신학회논문지
• /
• 제15권8호
• /
• pp.1805-1812
• /
• 2011

Bandpass sampling(BPS) 기술은 나이퀴스트(Nyquist) 샘플링 주파수보다 낮은 주파수를 사용하여 RF 대역의 신호를 직접 하향변환 할 수 있다는 장점을 가지고 있지만, 나이퀴스트 영역에서 self-image의 중복을 피하기 위해서는 샘플링 주파수의 선택에 제약이 따른다. 2개의 ADC를 사용하는 2차(second-order) BPS는 self-image를 제거하기 위한 신호처리가 추가 된다는 조건으로 샘플링 주파수의 선택이 자유롭다. 하지만 RF 대역이 바뀌면 신호처리를 위한 파라미타를 재구성해야 한다. 본 논문에서는 2차 BPS의 한 형태인 quadrature BPS의 구조를 가지면서, 재구성이 필요 없는 간단한 보상 필터만을 사용하여 임의 RF 대역으로부터 나이퀴스트 영역으로 하향 변환하는 complex BPS 기반의 SDR front-end에 대하여 기술한다.

• 한국전자통신학회논문지
• /
• 제7권1호
• /
• pp.15-20
• /
• 2012

본 논문에서는 디지털 마이크로파 통신 시스템 수신기의 동작범위(Dynamic Range) 향상을 위한 설계 방법을 K-band FEM(Front-End Module)에 적용하여 설계 및 분석하였다. 동작범위를 광범위하게 설계하기 위해 저 잡음 증폭기(LNA)의 잡음지수를 최소화하여 증폭된 입력신호 레벨을 최소화하는 방법을 제안하였으며, 주파수 변환은 높은 선택도(Q)와 안정도가 높은 위상고정 유전체 발진기(PL-DRO) 및 변환이득을 가지는 능동믹서로 구성하였다. 각각의 모듈을 집적화하여 측정한 결과 약 54dB의 변환이득(CG)과 1.3dB의 전제 잡음지수(NF)를 나타내었다.

• Journal of Power Electronics
• /
• 제15권1호
• /
• pp.202-215
• /
• 2015

This paper investigates the stability and performance of model predictive controlled active-front-end (AFE) rectifiers for energy storage systems, which has been increasingly applied in power distribution sectors and in renewable energy sources to ensure an uninterruptable power supply. The model predictive control (MPC) algorithm utilizes the discrete behavior of power converters to determine appropriate switching states by defining a cost function. The stability of the MPC algorithm is analyzed with the discrete z-domain response and the nonlinear simulation model. The results confirms that the control method of the active-front-end (AFE) rectifier is stable, and that is operates with an infinite gain margin and a very fast dynamic response. Moreover, the performance of the MPC controlled AFE rectifier is verified with a 3.0 kW experimental system. This shows that the MPC controlled AFE rectifier operates with a unity power factor, an acceptable THD (4.0 %) level for the input current and a very low DC voltage ripple. Finally, an efficiency comparison is performed between the MPC and the VOC-based PWM controllers for AFE rectifiers. This comparison demonstrates the effectiveness of the MPC controller.

• ETRI Journal
• /
• 제42권6호
• /
• pp.943-950
• /
• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• International journal of advanced smart convergence
• /
• 제10권1호
• /
• pp.12-23
• /
• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• Journal of Information Processing Systems
• /
• 제16권6호
• /
• pp.1372-1390
• /
• 2020

An attractive user interface (UI) design with a clear user experience (UX) is the key for the success of applications. Therefore software development projects require very close collaboration between SI developers and front-end service developers. However, methodologies for software development only exist with inadequate development processes or work standards for collaboration. This survey derived 13 risk factors in developing UI/UX from 113 risk factors of IT projects through a questionnaire and factor analysis and proposed a collaboration-based UI/UX development model that can eliminate or mitigate six risks with high weights and reliability. To extract risk factors with high reliability, factor and reliability were analyzed to extract 13 major risks, and based on the expert opinions and the results of correlation analysis, UI/UX development stages were classified into planning, design, and implementation. The causal relationships between risks were verified through regression analysis. This study is the first to expertly analyze major risks based on collaboration in UI/UX development and derive a theoretical basis that can be used in project risk management. These findings are expected to provide a basis for research on development methodologies for higher levels of front-end services and to construct rational collaboration systems between SI practitioners and front-end service providers.