• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.1
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• pp.40-45
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• 2013

The purpose of this study was to detect the pin hole defect of dental composite restoration using lock-in thermography method. Amplitude and phase images of the composite resin specimens were analyzed according to the lock-in frequency and the diameter of defect area. Through the amplitude image analysis, at lock-in frequency of 0.05 Hz, defect diameters 2-5 mm exhibited the highest amplitude contrast value between defective area and sound area. The lock-in frequency range of 0.3-0.5 Hz provided good phase angle contrast for the defect area. At lock-in frequency range of 0.5 Hz, defect diameter of 5 mm exhibited the highest phase contrast value. It is concluded that the infrared lock-in thermography method verified the effectiveness for detecting the pin hole defect of dental composite restoration.

• Journal of the Korean Society for Railway
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• v.20 no.4
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• pp.448-457
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• 2017

In this paper, for high speed railway propulsion systems, a single phase PWM Converter using discontinuous PWM (DPWM) was investigated. The conventional PWM Converter uses a low frequency modulation index of less than 10 to reduce switching losses due to high power characteristics, which results in low control frequency bandwidth and requires an additional compensation method. To solve these problems, the DPWM method, which is commonly used in three phase PWM Inverters, was adopted to a single phase PWM Converter. The proposed method was easily implemented using offset voltage techniques. Method can improve the control performance by doubling the frequency modulation index for the same switching loss, and can also bring the same dynamic characteristics among switches. Proposed DPWM method was verified by simulation of 100 kW PWM converter.

• Journal of Positioning, Navigation, and Timing
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• v.12 no.3
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• pp.245-255
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• 2023

Time comparison techniques are necessary for generating and keeping Coordinated Universal Time (UTC) and distributing standard time clocks. Global Navigation Satellite System (GNSS) Common View, GNSS All-in-View, Two-Way Satellite Time and Frequency Transfer (TWSTFT), Very Long Baseline Interferometry (VLBI), optical fiber, and Network Time Protocol (NTP) based methods have been used for time comparison. In these methods, GNSS based time comparison techniques are widely used for time synchronization in critical national infrastructures and in common areas of application such as finance, military, and wireless communication. However, GNSS-based time comparison techniques are vulnerable to jamming or interference environments and it is difficult to respond to GNSS signal disconnection according to the international situation. In response, in this paper, Code-Division Multiple Access (CDMA) based All-to-All TWSTFT operation method is proposed. A software-based simulation platform also was designed for performance analysis in multi-TWSTFT signal environments. Furthermore, code and carrier measurement jitters were calculated in multi-signal environments using the designed simulation platform. By using the technique proposed in this paper, it is anticipated that the TWSTFT-based time comparison method will be used in various fields and satisfy high-performance requirements such as those of a GNSS master station and power plant network reference station.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2370-2378
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• 2009

The enhanced phase angle estimation algorithm is essential to supply the power stably under synchronizing with grid source. In this paper, we are proposed the novel phase angle estimation algorithm and verified the validity of proposed method as simulation with PSIM and experiments. We sort the harmonics element using high-pass filter(HPF) that have the cut-off frequency below basic element and make reverse d-q transformation. So, it can be restored the harmonics element at stationary axis, and we can get the fundamental voltage element of AC grid. Proposed PLL method have a rapid responsibility and a large margin at controller design than conventional method because it have a small phase delay and a sufficient controller gain margin. And, it can reduce the error of voltage rms value and axis transformation according to robust PLL algorithm against the harmonic and phase unbalance.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.649-659
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• 2003

OFDM/FH communication system Is widely used in the wireless communication for the large capacity and high-speed data transmission. However, phase noise and PAPR (peak-to-average power ratio) are the serious problems causing performance impairment. In this paper, PLL (phase locked loop) frequency synthesizer with high switching speed is used for the phase noise model. SSPA and TWTA are considered for the nonlinear HPA model. Under these conditions and by approximating $e^{j{\phi}[m]}$ into $1 + j{\phi}[m]-\frac{1}{2}{\phi}^2[m]$ for the phase noise nonlinear approximation, SINR (signal-to-interference-noise-ratio) with nonlinear HPA and phase noise is derived in the OFDM/FH system. The bit error probabilities (BER) are found by computer simulation method and semi-analytical method. The simulation results closely match with the semi-analytical results.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 1998.11a
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• pp.111-115
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• 1998

A phase-shifting projection moire method particularly intended for high-speed three-dimensional shape reconstruction of diffuse objects is presented. Emphasis is on realization of phase-shifting fringe analysis in projection moire topography using a set of line grating pairs designed to provide different phase shifts in sequence. Further a time-integral fringe capturing scheme is devised to remove undesirable high frequency original grating patterns in real-time without time-consuming software image processing. Finally the performances of the proposed method are discussed with measurement results.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.430-432
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• 2005

This paper presents a novel, single stage, isolated, three-phase switching rectifier capable of switching at high frequency. The circuit topology Provides zero-voltage switching for all switches, output voltage regulation, unity input power factor, all in a single power conversion stage. Operating principle and experimental results in the 48V/100A DC power supply of three-phase single stage method are presented.