• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Progress in Superconductivity
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• v.8 no.1
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• pp.33-39
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• 2006

We have developed a second-order double relaxation oscillation SQUID(DROS) gradiometer with a baseline of 35 mm, and constructed a poorly magnetically-shielded room(MSR) with an aluminum layer and permalloy layers for magnetocardiography(MCG). The 2nd-order DROS gradiometer has a noise level of 20 $fT/{\surd}Hz$ at 1 Hz and 8 $fT/{\surd}Hz$ at 200 Hz inside the heavily-shielded MSR with a shielding factor of $10^3$ at 1 Hz and $10^4-10^5$ at 100 Hz. The poorly-shielded MSR, built of a 12-mm-thick aluminum layer and 4-6 permalloy layers of 0.35 mm thickness, is 2.4mx2.4mx2.4m in size, and has a shielding factor of 40 at 1 Hz, $10^4$ at 100 Hz. Our 64-channel second-order gradiometer MCG system consists of 64 2nd-order DROS gradiometers, flux-locked loop electronics, and analog signal processors. With the 2nd-order DROS gradiometers and flux-locked loop electronics installed inside the poorly-shielded MSR, and with the analog signal processor installed outside it, the noise level was measured to be 20 $fT/{\surd}Hz$ at 1 Hz and 8 $fT/{\surd}Hz$ at 200 Hz on the average even though the MSR door is open. This result leads to a low noise level, low enough to obtain a human MCG at the same level as that measured in the heavily-shielded MSR. However, filters or active shielding is needed fur clear MCG when there is large low-frequency noise from heavy air conditioning or large ac power consumption near the poorly-shielded MSR.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.990-992
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• 2002

30kW electrical power conversion system is delveloped for the variable speed wind turbine system. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and frequency of generator output vary according to the wind speed, a dc/dc boosting chopper is utilized to maintain constant dc link voltage. Grid connection type PWM inverter supply currents into the utility line by regulating the dc link voltage. The active power is controlled by q-axis current which the reactive power can be controlled by d-axis current reference change. The phase angle of utility voltage is detected using s/w PLL(Phased Locked Loop) in d-q synchronous reference frame. This scheme gives a low cost power solution for variable speed WECS.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1375-1386
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• 2016

To decouple the secondary saliencies in sensorless permanent magnet synchronous machine (PMSM) drives, a repetitive control (RC) in the angle domain is proposed. In this paper, the inductance model of a concentrated windings surface-mounted PMSM (cwSPMSM) with strong secondary saliencies is developed. Due to the secondary saliencies, the estimated position contains harmonic disturbances that are periodic relative to the angular position. Through a transformation from the time domain to the angle domain, these varying frequency disturbances can be treated as constant periodic disturbances. The proposed angle-domain RC is plugged into an existing phase-locked loop (PLL) and utilizes the error of the PLL to generate signals to suppress these periodic disturbances. A stability analysis and parameter design guidelines of the RC are addressed in detail. Finally, the proposed method is carried out on a cwSPMSM drive test-bench. The effectiveness and accuracy are verified by experimental results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.

• Progress in Superconductivity
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• v.5 no.2
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• pp.94-97
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• 2004

Step-edge Josephson junctions (SEJ) have been fabricated on sapphire substrates with in situ deposited films of CeO$_2$ buffer layer and YBa$_2$Cu$_3$O$_{7}$ films on the low angle steps. Direct coupled SQUID magnetometers with the SEJ were formed on 1 cm X 1 cm R-plane sapphire substrates. Typical 5-${\mu}{\textrm}{m}$-wide Josephson junctions have R$_{N}$ of 3 Ω and I$_{c}$ of 50 $mutextrm{A}$ at 77 K. The direct coupled SQUID magnetometers were designed to have pickup coils of 50-${\mu}{\textrm}{m}$-wide 16 parallel loops on the 1 cm X 1 cm substrates with outer dimension of 8.8 mm X 8.8 mm. The SEJ SQUID magnetometers exhibit relatively low 1/f noise even with dc bias control, and could be stably controlled by flux-locked loops in the magnetically disturbed environment. Field noise of the do SQUID was measured to be 200∼300 fT/Hz$^{1}$2/in the white noise region and about 2 pT/Hz$^{1}$2/ at 1 Hz when measured with dc bias method.hod.d.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.179-187
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• 2010

This paper proposes a new anti-islanding method for single-phase grid-connected photovoltaic (PV) systems using Goertzel algorithm. The proposed scheme is based on inducing increases or decreases of frequencies of load voltage and current that is in the form of existences or periodical variations of the reactive power components. The frequency detection is needed to apply this power variation method to the grid-connected power converter. The proposed method is able to get a fast detection for anti-islanding without the effect of harmonics and noises. The simulation and experiment results validate the effectiveness of the proposed method.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.564-566
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• 2003

전력 계통에서 안정한 전력을 공급하는 것은 매우 중요하다. 전력 계통의 오류는 전압 및 주파수를 감시함으로써 검출 가능하다. 본 논문에서는 디지털 위상 고정 루프를 이용한 전력 계통의 주파수 측정 장치를 제안하고 이를 구현한 결과를 제시하고자 한다. 제안한 주파수 측정 장치는 위상 고정 루프의 기본요소로 구성된다. 위상분별기는 배타적 논리연산을 통해 위상오차를 검출하고 위상의 앞섬 및 뒤짐의 검출이 가능하도록 설계하였으며, 전력 계통의 주파수 동특성을 고려해서 3차의 루프 필터를 설계하였다. DCO는 출력 주파수의 분해능을 고려하여 입력 신호를 정확하게 추정할 수 있도록 설계하였다. 제안한 주파수 측정 장치의 성능을 검증하기 위하여 모의실험을 통해 주파수 변동량의 측정 범위 및 정확도를 검토하였으며, FPGA와 CPU를 포함하는 하드웨어를 구현하였다. FPGA에는 Verilog HDL로 디지털 위상 고정 루프의 위상분별기와 DCO를 구현하였으며 루프필터는 소프트웨어로 구현하였다. 제안한 디지털 위상 고정 루프의 성능 검증을 위해 정밀한 함수 발생기의 출력을 인가한 후 출력 주파수를 측정한 결과 및 전력 계통에 대한 실험 결과를 제시하였다.