• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.482-484
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• 2006

This paper describes fast-hopping frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432MHz, 3960MHz, 4488MHz) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224MHz. The second uses three PLLs operating at corresponding center frequencies. The third employes two PLLs operating at 3960MHz and 528MHz. Simulation results using a 0.18um RF CMOS process parameters show that the third structure exhibit the best characteristics. The band switching time of the proposed synthesizer is less than 1.3ns and the spur is less than -36dBc. The synthesizer consumes 22mA from a 1.8V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1059-1067
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• 1996

A 128/129 dual-modulus prescalar IC is designed for application to frequency synthesizers in high frequency communication systems. The FET logic used in this design is SCFL(Source Coupled FET Logic), employing depletion-mode 1.mu.m gate length GaAs MESFETs with the threshold voltage of -1.5V. This circuit consists of 8 flip-flops, 3 OR gates, 2 NOR gates, a modulus control buffer and I/O buffers, which are integrated with about 440 GaAs MESFETs on dimensions of 1.8mm. For $V_{DD}$ and $V_{SS}$ power supply voltages 5V and -3.3V Commonly used in TTL and ECL circuits are determined, respectively. The simulation results taking into account the threshold voltage variation of .+-.0.2V and the power supply variation of .+-.1V demonstrate that the designed prescalar can operate up to 2GHz. This prescalar is fabricated using the ETRI MMIC foundary process and the measured maximum operating frquency is 621MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• Journal of IKEEE
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• v.17 no.1
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• pp.16-21
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• 2013

Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.536-542
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• 2004

An architecture of direct digital frequency synthesizers (DDFS) is studied in this paper The Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. In this paper, we suggest three new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another techniques use simple interpolation techniques combined with hierarchical ROM structures. A 12 bit sine wave is generated by using these techniques. Experimental results show that the new proposed techniques can reduce the required ROM size by up to 24%, when compared to that of a resent method[1].

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.951-954
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• 1999

A direct digital frequency synthesizer is designed in full custom method using 0.65${\mu}{\textrm}{m}$ CMOS n-well technology The chip provides the capability of the parallel operation using up to 4 chips with an operation frequency of 440MHz. The generated waveform can be modulated by various modulation techniques such as QPSK, 256 . 64. 32 . 16 QAM and FM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.873-879
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• 2016

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.267-270
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• 1999

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.818-824
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• 2011

In this paper, we proposed a phase noise model of a frequency synthesizer for a radar system. Especially, it was proposed a phase noise model in a DAS(Direct Analog Synthesizer) and a frequency up converter system using Leeson's model. The proposed phase noise model was derived from the measurement data of model 1 and evaluated by adapting to model 2 and model 3 frequency synthesizers. The prediction phase noise by modeling was totally matched to the measured data and the effective analysis of the phase noise was done in a frequency synthesizer and a frequency converter of radar system.