• Title/Summary/Keyword: frequency of using

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Selective Dual Duty Cycle Controlled High Frequency Inverter Using a Resonant Capacitor in Parallel with an Auxiliary Reverse Blocking Switch

  • Saha, Bishwajit;Suh, Ki-Young;Kwon, Soon-Kurl;Mishima, Tomokazu;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • v.7 no.2
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    • pp.118-123
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    • 2007
  • This paper presents a new ZCS-PWM high frequency inverter. Zero current switching operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. Dual duty cycle control scheme is used to provide a wide range of high frequency AC output power regulation that is important in many high frequency inverter applications. It found that a complete soft switching operation can be achieved even for low power setting ranges by introducing high-frequency dual duty cycle control scheme. The proposed high frequency inverter is more suitable for consumer induction heating(IH) applications. The operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

A 166MHz Phase-locked Loop-based Frequency Synthesizer (166MHz 위상 고정 루프 기반 주파수 합성기)

  • Minjun, Cho;Changmin, Song;Young-Chan, Jang
    • Journal of IKEEE
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    • v.26 no.4
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    • pp.714-721
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    • 2022
  • A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

Diagnosis of chatter by using the chatter frequency-spindle speed diagram (채터 주파수-회전 속도 선도를 이용한 채터 진단에 관한 연구)

  • 이상호;이대형;박중윤;홍성욱
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2000.11a
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    • pp.261-264
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    • 2000
  • This paper presents a method to identify the on-set of chatter by using the chatter frequency-spindle speed diagram for a milling spindle-workpiece system in face milling process. To this purpose, the eigenvalue problem approach using frequency response function is adopted for predicting both the chatter condition and chatter frequency. The chatter frequency -spindle speed diagram for various conditions is investigated throughout simulation and experiment to diagnose the chatter. The simulation and experimental results show that the chatter frequency-spindle speed diagram is useful for diagnosis of the on-set of chatter vibration.

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Optimization of Diode-pumped Cesium Vapor Laser Using Frequency Locked Pump Laser

  • Hong, Seongjin;Kong, Byungjoo;Lee, Yong Soo;Oh, Kyunghwan
    • Current Optics and Photonics
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    • v.2 no.5
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    • pp.443-447
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    • 2018
  • We propose a diode-pumped cesium laser using frequency locking of a pump laser that can effectively increase the maximum output power of the cesium laser. We simultaneously monitored the absorption spectrum of cesium and the laser output power, and the frequency of pump laser was locked at the center of the $D_2$ absorption line of the cesium atom to obtain an effective gain enhancement. Using this scheme, we have achieved output power increase of ~0.1 W compared to when frequency locking was not applied. Furthermore, by optimizing the temperature of the cesium cell and the reflectivity of the output coupler, we successfully achieved an output power of 1.4 W using the pump power of 2.9 W, providing a slope efficiency of 61.5% and optical-to-optical efficiency of 49%.

A Low Close-in Phase Noise 2.4 GHz RF Hybrid Oscillator using a Frequency Multiplier

  • Moon, Hyunwon
    • Journal of Korea Society of Industrial Information Systems
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    • v.20 no.1
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    • pp.49-55
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    • 2015
  • This paper proposes a 2.4 GHz RF oscillator with a very low close-in phase noise performance. This is composed of a low frequency crystal oscillator and three frequency multipliers such as two doubler (X2) and one tripler (X3). The proposed oscillator is implemented as a hybrid type circuit design using a discrete silicon bipolar transistor. The measurement results of the proposed oscillator structure show -115 dBc/Hz close-in phase noise at 10 kHz offset frequency, while only dissipating 5 mW from a 1-V supply. Its close-in phase noise level is very close to that of a low frequency crystal oscillator with little degradation of noise performance. The proposed structure which is consisted of a low frequency crystal oscillator and a frequency multiplier provides new method to implement a low power low close-in phase noise RF local oscillator.

Low-Power Frequency Offset Synchronization Block Design and Implementation using Pipeline CORDIC (Pipeline CORDIC을 이용한 저전력 주파수 옵셋 동기화기 설계 및 구현)

  • Ha, Jun-Hyung;Jung, Yo-Sung;Cho, Yong-Hoon;Jang, Young-Beom
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.10
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    • pp.49-56
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    • 2010
  • In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

High Frequency Circuit Design using Feedback Control with Body Load Fluctuation for Pain Relief Therapy (통증 완화 치료기용 인체 부하 변동에 따른 피드백 제어가 가능한 고주파 회로 설계)

  • Park, Chul-Won;Won, Chul-Hee
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.62 no.1
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    • pp.45-49
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    • 2013
  • High frequency system has been used for the purpose of skin care and obesity treatment, by high-frequency energy is applied to the human body generates deep heat. Conventional high frequency system could not selection control by depending on the body load fluctuations. Such as burns and side effects have been reported by system instability and then therapeutic effect is insufficient. During treatment, objective information about the status of the patient was no. Because of treatment methods are subjective, and so tailored treatments were impossible. In this paper, high frequency medical system with sinusoidal frequency characteristics without distortion of the Push pull switching scheme for pain relief therapy was designed. And control circuit that was designed by feedback using the output changes according to the body-load fluctuation. Last, power circuit for efficient control the heat generated from the hardware was proposed.

Design of Low Power System using Dynamic Scaling (Dynamic Scaling을 이용한 저전력 시스템의 설계)

  • Kim, Do-Hun;Kim, Yang-Mo;Kim, Seung-Ho;Lee, Nam Ho
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.282-285
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    • 2002
  • In this paper, we designed of low power system by using dynamic scaling. As an effective low-power design, dynamic voltage/frequency scaling recently has received a lot of attention. In dynamic frequency scheme, all execution cycles are driven by the clock frequency that switched frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and higher frequency operators to later steps. This algorithm assigned the frequency for each execution cycle then it adjusted the voltage associated with the frequency.

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Defect classification of refrigerant compressor using variance estimation of the transfer function between pressure pulsation and shell acceleration

  • Kim, Yeon-Woo;Jeong, Weui-Bong
    • Smart Structures and Systems
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    • v.25 no.2
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    • pp.255-264
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    • 2020
  • This paper deals with a defect classification technique that considers the structural characteristics of a refrigerant compressor. First, the pressure pulsation of the refrigerant flowing in the suction pipe of a normal compressor was measured at the same time as the acceleration of the shell surface, and then the transfer function between the two signals was estimated. Next, the frequency-weighted acceleration signals of the defect classification target compressors were generated using the estimated transfer function. The estimation of the variance of the transfer function is presented to formulate the frequency-weighted acceleration signals. The estimated frequency-weighted accelerations were applied to defect classification using frequency-domain features. Experiments were performed using commercial compressors to verify the technique. The results confirmed that it is possible to perform an effective defect classification of the refrigerant compressor by the shell surface acceleration of the compressor. The proposed method could make it possible to improve the total inspection performance for compressors in a mass-production line.

Design of Wideband Microwave Absorbers Using Reactive Salisbury Screens with Maximum Flat Reflection

  • Kim, Gunyoung;Kim, Sanghoek;Lee, Bomson
    • Journal of electromagnetic engineering and science
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    • v.19 no.2
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    • pp.71-81
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    • 2019
  • This paper presents a design methodology for wideband single-layered microwave absorbers with arbitrary absorption at the design center frequency using reactive Salisbury screens. The bandwidth of the absorber increases when the flatness of the reflection response at the design center frequency is maximized. Based on this observation, closed-form design formulas for wideband absorbers are derived. As they are scalable to any design frequency, wideband reactive screens can be systematically realized using two-dimensional periodic crossed-dipole structures patterned on a resistive sheet. Based on this method, a single-layered absorber with a 90% bandwidth improved to 124% of the design center frequency is presented. For the purpose of physical demonstration, an absorber with a design center frequency of 10 GHz is designed and fabricated using a silver nanowire resistive film with a surface resistance of 30 Ω/square. The measured absorption shows a good agreement with both the calculation and the electromagnetic simulation.