• ETRI Journal
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• v.35 no.2
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• pp.218-225
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• 2013

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.343-345
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• 2013

This paper describes a phase-locked loop (PLL) that generates a 51-phase clock with the operating frequency of 125MHz. To generate 51-phase clock with a frequency of 125 MHz, the proposed PLL uses three voltage controlled oscillators (VCOs) which are connected by resistors. Each VCO consists of 17 delay-cells. An resistor averaging scheme, which makes three VCOs to connect with each other, makes it possible to generates 51-phase clock of the same phase difference. The proposed PLL is designed by using 65 nm CMOS process with a 1.0 V supply. At the operating frequency of 125 MHz, the simulated DNL and peak-to-peak jitter are +0.0016/-0.0020 LSB and 1.07 ps, respectively. The area and power consumption of the implemented PLL are $290{\times}260{\mu}m^2$ and 2.5 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.73-81
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• 2012

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.135-136
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• 2008

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1973-1981
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• 1994

A PLDRO(Phase Locked Dielectric Resonator Oscillator) in Ku-band(10.95-11.70GHz) is designed with the concept of the feedback property of PLL(Phase Locked Loop). A series feedback type DRO is developed, and VCDRO(Voltage Controlled Dielectric Resonator Oscillator) using a varactor diode as a voltage-variable capacitor is implemented to tune oscillating frequency electrically. Then, PLDRO is designed by using a SPD(Sampling Phase Detector). This PLDRO is phase-locked voltage controlled DRO to reference source(VHF band) by SPD at 10.00 GHz for European FSS(Fixed Satellite Service). The PLDRO generates output power greater than 10dBm at 10.00 GHz and has phase noise of -80 dBc/Hz at 10 KHz offset from carrier. This PLDRO achieves much better frequency stability than conventional VCDRO.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1347-1356
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• 2018

In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from $-{\pi}$ to ${\pi}$. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.