• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.1-6
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• 2010

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a $4{\times}4$ sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and the requirement of high data bandwidth and high performance processing units. We propose adaptive pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. Parameters and coefficients are delivered using hand-shaking communication through dedicated interconnections and frame pixel data are transferred using AMBA AHB network. The processing time of each block is variable depending on the characteristics of images, and the processing units start to work whenever they are ready. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2C
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• pp.110-120
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• 2003

In this paper, we propose a Multiresolution Motion Estimation(MRME) adapted to Low-Band-Shift(LBS) method in wavelet domain. To overcome shift-variant property on wavelet coefficients, the LBS was previously proposed. This method which is applied to reference frame in video coding technique, has superior performance in terms of rate-distortion characteristic. However, this method needs more memory and computational complexity. In this paper, The computational complexity of the proposed method(LBS-MRME) is about 15.6% of that of existing method at 3-level wavelet transform. And although it has about 7 times as much as existing method's motion vector since each subband has different motion vector, it decreases motion compensated prediction error by detailed motion estimation, and then has better efficient coding performance. The experimental results with the proposed method showed about 0.3∼11.6% improvement of MAD performance in case of lossless coding, and 0.3∼3.0㏈ improvement of PSNR performance at the same bit rate in case of lossy coding.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.46-52
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• 1998

In this paper, after inputting the computer with the attached number plate on the vehicle, using it, the color decomposition method and back propagation neural network proposed the extractable method of the vehicle number plate at high speed. This method separated R, G, B signal form input moving vehicle image to computer through video camera, then after transform this R, G, B signal into input image data of the computer by using color depth of vehicle number plate and store up binary value in the memory frame buffer. After adapting character's recognition algorithm, also improving this, by adapting back propagation neural network makes the vehicle number plate recognition system. Also minimalizing the similar color's confusion, adapting horizontal and vertical extracting algorithm by using the vehicle's rectangular architecture shows the extract and character's recognition of the vehicle number plate at high speed.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.57-64
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• 2009

This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.16-33
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• 1993

New decoding algorithm of double-error-correction Reed-Solmon codes over GF(2$^{8}$) for optical compact disks is proposed and decoding algorithm of RS codes with triple-error-correcting capability is presented in this paper. First of all. efficient algorithms for estimating the number of errors in the received code words are presented. The most complex circuits in the RS decoder are parts for soving the error-location numbers from error-location polynomial, so the complexity of those circuits has a great influence on overall decoder complexity. One of the most known algorithm for searching the error-location number is Chien's method, in which all the elements of GF(2$^{m}$) are substituted into the error-location polynomial and the error-location number can be found as the elements satisfying the error-location polynomial. But Chien's scheme needs another 1 frame delay in the decoder, which reduces decoding speed as well as require more stroage circuits for the received ocode symbols. The ther is Polkinghorn method, in which the roots can be resolved directly by solving the error-location polynomial. Bur this method needs additional ROM (readonly memory) for storing tthe roots of the all possible coefficients of error-location polynomial or much more complex cicuit. Simple, efficient, and high speed method for solving the error-location number and decoding algorithm of double-error correction RS codes which reudce considerably the complexity of decoder are proposed by using Hilbert theorems in this paper. And the performance of the proposed decoding algorithm is compared with that of conventional decoding algorithms. As a result of comparison, the proposed decoding algorithm is superior to the conventional decoding algorithm with respect to decoding delay and decoder complexity. And decoding algorithm of RS codes with triple-error-correcting capability is presented, which is suitable for error-correction in digital audio tape, also.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.1
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• pp.74-81
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• 2003

In this study, we'd implemented a real time embedded speech recognition system that requires minimum memory size for speech recognition engine and DB. The word to be recognized consist of 40 commands used in a PCS phone and 10 digits. The speech data spoken by 15 male and 15 female speakers was recorded and analyzed by short time analysis method, which window size is 256. The LPC parameters of each frame were computed through Levinson-Burbin algorithm and they were transformed to Cepstrum parameters. Before the analysis, speech data should be processed by pre-emphasis that will remove the DC component in speech and emphasize high frequency band. Baum-Welch reestimation algorithm was used for the training of HMM. In test phone, we could get a recognition rate using likelihood method. We implemented an embedded system by porting the speech recognition engine on ARM core evaluation board. The overall recognition rate of this system was 95%, while the rate on 40 commands was 96% and that 10 digits was 94%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1055-1061
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• 2008

H.264 is the prominent video coding standard in various applications such as real-time streaming and digital multimedia broadcasting, since it provides enhanced compression performance, error resilience tools, and network adaptation. Compression efficiency of H.264 has been improved, however, it requires more computing and memory access than traditional methods. In this paper we proposed adaptive intra fast algorithm for real-time video surveillance system reducing the encoding complexity of H264/A VC. For this aim, temporal interrelationship between macroblock in the previous and the current frame is used to decide the encoding mode of macroblock fast. As a result, though video quality was deteriorated a little, less than 0.04dB, and bit rate was somewhat increased in suggested method, however, proposed method improved encoding time significantly and, in particular, encoding time of an image with little changes of neighboring background such as surveillance video was more shortened than traditional methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.313-315
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• 2010

In this paper, we describe research results of developing hardware rasterizer that is applicable to mobile 3D graphics system, designed in SIMD architecture and verified in FPGA. Tile-based scan conversion unit is designed like SIMD architecture running four tiles simultaneously and each tile traverses pixels hierarchical in 3-level so that visiting counts is minimized. As experimental results, $8{\times}8$ is the most efficient size of tile and the last step of tile traversing is performed on $2{\times}2$ sized subtile. The rasterizer supports flat shading and gouraud shading and texture mapper supports affine mapping and perspective corrected mapping. Also, texture mapper supports point sampling mode and bilinear interpolating sampling mode and two types of wrapping modes and various blending modes. The rasterzer operates as 120Mhz on xilinx vertex4 $l{\times}100$ device. To easy verification, texture memory and frame buffer are generated as block rom and block ram.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.

• Korean Journal of Remote Sensing
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• v.4 no.1
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• pp.31-40
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• 1988

Low-cost microcomputer systems can be assembled which possess computing power, color display, memory, and storage capacity approximately equal to graphic workstactions. A low-cost, flexible, and user-friendly IBM/PC/XT/AT based image processing system has been developed and named as KMIPS(KAIST (Korea Advanced Institute of Science & Technology) Map and Image Processing Station). It can be easily utilized by the resource managers who are not computer specialists. This system can: * directly access Landsat MSS and TM, SPOT, NOAA AVHRR, MOS-1 satellite imagery and other imagery from different sources via magnetic tape drive connected with IBM/PC; * extract image up to 1024 line by 1024 column and display it up to 480 line by 672 column with 512 colors simultaneously available; * digitize photographs using a frame grabber subsystem(512 by 512 picture elements); * perform a variety of image analyses, GIS and terrain analyses, and display functions; and * generate map and hard copies to the various scales. All raster data input to the microcomputer system is geographically referenced to the topographic map series in any rater cell size selected by the user. This map oriented, georeferenced approach of this system enables user to create a very accurately registered(.+-.1 picture element), multivariable, multitemporal data sets which can be subsequently subsequently subjected to various analyses and display functions.