• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.71-74
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+PlusII and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.11-23
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL, simulated on Max+plus Ⅱ , and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation techniques according to simulation results and implementation.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.04a
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• pp.91-95
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats to a target format. Circuits for the conversion has been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+Plus II and implemented with an FPGA cpip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• Genomics & Informatics
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• v.8 no.2
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• pp.97-99
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• 2010

To allow for a quick conversion of the proprietary sequence data from various sequencing platforms, sequence format conversion toolkits are required that can be easily integrated into workflow systems. In this respect, a format conversion tool, as well as quality conversion tool would be the minimum requirements to integrate reads from different platforms. We have developed the Pyrus NGS Sequencing Format Converter, a simple software toolkit which allows to convert three kinds of Next Generation Sequencing reads, into commonly used fasta or fastq formats. The converter modules are all implemented, uniformly, in Java GUI modules that can be integrated in software applications for displaying the data content in the same format.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1137-1143
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• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• Transactions of the Korean Society of Automotive Engineers
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• v.5 no.5
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• pp.197-212
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• 1997

The performance of a torque converter can be expressed by the performance parameters such as flow radius and flow angle, on the mean flow path. The geometric analysis of the torque converter is required to determine these parameters for the modeling of the torque converter. In general, the blade shape is depicted by three dimensional data at the mid-surface of blade or those of the pressure and suction side. To generate three dimensional model of the blade using the data mentioned above, a consistent data format and a shape generation algorithm are required. This paper presents a useful consistent data format of the blades and an algorithm for the geometrical shape generation. By the geometric analysis program to which the shape generation algorithm is embedded, the variation of blade angles in rotating element analyzed. Then finally, the analyzed results of geometric profile of a blade are compared with those of the blade design principle, so called forced vortex theorem.

• The Journal of Korean Association of Computer Education
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• v.7 no.6
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• pp.141-150
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• 2004

The method of reusing the environmental data which is previously modelled in modeling and simulation is very important. So, we need an environmental data representation and interchange mechanism which satisfies the requirements of sharing. The SEDRIS STF(SEDRIS Transmittal Format) provides environmental data users and producers with a clearly defined interchange specification. In this paper, We design and implement an automatic converter which converts commercial data(Maya) format to standard interchange format and vice verse without losing semantic of information content using SEDRIS standard interchange format.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.