• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.71-74
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+PlusII and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• 한국시뮬레이션학회논문지
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• 제9권4호
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• pp.11-23
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL, simulated on Max+plus Ⅱ , and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation techniques according to simulation results and implementation.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2000년도 춘계학술대회 논문집
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• pp.91-95
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats to a target format. Circuits for the conversion has been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+Plus II and implemented with an FPGA cpip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• Genomics & Informatics
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• 제8권2호
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• pp.97-99
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• 2010

To allow for a quick conversion of the proprietary sequence data from various sequencing platforms, sequence format conversion toolkits are required that can be easily integrated into workflow systems. In this respect, a format conversion tool, as well as quality conversion tool would be the minimum requirements to integrate reads from different platforms. We have developed the Pyrus NGS Sequencing Format Converter, a simple software toolkit which allows to convert three kinds of Next Generation Sequencing reads, into commonly used fasta or fastq formats. The converter modules are all implemented, uniformly, in Java GUI modules that can be integrated in software applications for displaying the data content in the same format.

• 제어로봇시스템학회논문지
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• 제15권11호
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• pp.1137-1143
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• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• 한국시뮬레이션학회논문지
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• 제10권3호
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• 한국자동차공학회논문집
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• 제5권5호
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• pp.197-212
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• 1997

The performance of a torque converter can be expressed by the performance parameters such as flow radius and flow angle, on the mean flow path. The geometric analysis of the torque converter is required to determine these parameters for the modeling of the torque converter. In general, the blade shape is depicted by three dimensional data at the mid-surface of blade or those of the pressure and suction side. To generate three dimensional model of the blade using the data mentioned above, a consistent data format and a shape generation algorithm are required. This paper presents a useful consistent data format of the blades and an algorithm for the geometrical shape generation. By the geometric analysis program to which the shape generation algorithm is embedded, the variation of blade angles in rotating element analyzed. Then finally, the analyzed results of geometric profile of a blade are compared with those of the blade design principle, so called forced vortex theorem.

• 컴퓨터교육학회논문지
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• 제7권6호
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• pp.141-150
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• 2004

모델링 및 시뮬레이션 분야에서 이미 모델링되어 있는 환경 데이터를 재사용하고 확장할 수 있는 방법은 매우 중요하다. 이에 환경데이터의 공유 필요성을 만족할 수 있도록 확장될 수 있는 환경 데이터 표현 및 교환 메카니즘이 절대적으로 필요하다고 할 수 있다. SEDRIS의 STF(SEDRIS Transmittal Format)는 이러한 목적을 가능케 하는 표준으로써, 환경 데이터 사용자 및 생성자에게 명료하게 정의된 교환 명세를 제공한다. 본 논문에서는 SEDRIS의 표준 교환 포맷을 이용하여 상용 포맷(Maya)을 정보 내용의 의미 손실 없이 교환 포맷으로, 교환 포맷을 상용 포맷으로 변환하기 위한 자동변환기를 설계 및 구현하였다.

• 정보처리학회논문지A
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• 제9A권2호
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• pp.259-266
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• 2002

본 논문에서는 포맷 변환기를 사용하여 여러 가지 화상처리 필터링을 구현하였다. 이러한 설계 기법은 집적회로를 이용한 대규모 화소처리 배열을 근거로 하여 실현하였다. 집적구조의 두가지 형태는 연산병렬프로세서와 병렬 프로세스 DRAM(또는 SRAM) 셀로 분류할 수 시다. 1비트 논리의 설계 피치는 집적 구조에서의 고밀도 PE를 배열하기 위한 메모리 셀 피치와 동일하다. 이러한 포맷 변환기 설계는 효율적인 제어 경로 수행 능력을 가지고 있으며 하드웨어를 복잡하게 할 필요 없이 고급 기술로 사용 될 수 있다. 배열 명령어의 순차는 프로세스가 시작되기 전에 주 컴퓨터에 의해 생성이 되며 명령은 유니트 제어기에 저장이 된다. 주 컴퓨터는 프로세싱이 시작된 후에 저장된 명령어위치에서 시작하여 화소-병렬 동작을 처리하게 된다. 실험 결과 1) 단순한 평활화는 더 높은 공간의 주파수를 억제하면서 잡음을 감소시킬 뿐 아니라 에지를 흐리게 할 수 있으며, 2) 평활화와 분할 과정은 날카로운 에지를 보존하면서 잡음을 감소시키고, 3) 메디안 필터링기법은 화상 잡음을 줄이기 위해 적용될 수 있고 날카로운 에지는 유지하면서 스파이크 성분을 제거하고 화소 값에서 단조로운 변화를 유지 할 수 있었다.