• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.630-634
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• 2003

This paper proposes a Carrier-Rotation PWM technique that is new solution for the voltage unbalancing problem of flying capacitors in the Flying Capacitor Multi-level Inverter (FCMI).The proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of flying capacitors during one switching period of all the switches. it also has the same switch utilization and the reduced harmonics of output voltage. Hence, it is more suitable for the FCMI compared with the conventional solutions. Experimental results on the laboratory prototype flying capacitor 3-level inverter confirm the validity of the proposed PWM technique.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.281-285
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• 2001

This paper proposes a snubber circuit for flying capacitor multilevel inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber unit. It has such an advantage of Undeland snubber used in the two-level inverter. Compared with conventional RLD/RCD snubber for multilevel inverter and converter, the proposed snubber keeps such good features as fewer number of components, reduction of voltage stress of main switching devices due to low overvoltage, and improved efficiency of system due to low snubber loss. In this paper. the proposed snubber is applied to three-level flying capacitor inverter and its feature is demonstrated by computer simulation and experimental result.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.606-610
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• 2003

This paper presents a simple carrier symmetric method for the voltage balance of flying capacitors in FCMLI(flying capacitor multi-level inverter). To achieve the voltage balance of flying capacitors, the utilization of each carrier must be balanced during a half-cycle of the switching period such as PSPWM(Phase-Shifted PWM). However, the CRPWM(Carrier Redistribution PWM) method causes the fluctuation of flying capacitor voltages because the balanced utilization of carriers is not achieved. Moreover, it does not consider that the load current change has an influence on flying capacitor voltages by assuming that the current flows Into the load. To overcome the drawbacks of CRPWM, it is modified by the technique that carriers of each band are disposed symmetrically at every fundamental period. Firstly, the CRPWN method is reviewed and the theory on voltage balance of flying capacitors is analyzed. The proposed method Is introduced and is verified through the experiment result.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.337-343
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• 2015

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.316-317
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• 2020

In this paper, a novel six-level inverter is proposed. Voltage regulation is applied at DC-link and flying capacitors through the implementation of phase-shifted carrier-based modulation with zero-sequence voltage injection. The performance of the proposed structure has been verified under various modulation indices, where low voltage ripple is achieved at each capacitor and total harmonic distortions (THD) of line voltage at unity modulation index is about 15.95%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.451-462
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• 2016

Photovoltaic energy conversion becomes main focus of many researches due to its promising potential as source for future electricity and has many advantages than the other alternative energy sources like wind, solar, ocean, biomass, geothermal etc. In Photovoltaic power generation multilevel inverters play a vital role in power conversion. The three different topologies, diode-clamped (neutral-point clamped) inverter, capacitor-clamped (flying capacitor) inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each pv array can act as a separate dc source for each h-bridge module. This paper presents a single phase Cascaded H-bridge five level inverter for grid-connected photovoltaic application using sinusoidal pulse width modulation technique. This inverter output voltage waveform reduces the harmonics in the generated current and the filtering effort at the input. The control strategy allows the independent control of each dc-link voltages and tracks the maximum power point of PV strings. This topology can inject to the grid sinusoidal input currents with unity power factor and achieves low harmonic distortion. A PID control algorithm is implemented in Arm Processor LPC2148. The validity of the proposed inverter is verified through simulation and is implemented in a single phase 100W prototype. The results of hardware are compared with simulation results. The proposed system offers improved performance over conventional three level inverter in terms of THD.

• Journal of Power Electronics
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• v.14 no.2
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.333-334
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• 2015

본 논문은 단상 플라잉 커패시터 멀티레벨 인버터에서의 스위칭 상태 변화 횟수를 줄이는 새로운 기법을 제안하였다. 제안한 방법은 플라잉 커패시터 멀티레벨 인버터가 갖는 Redundant state 특성을 이용하며, 플라잉 커패시터 전압이 제어되는 범위 내에서 각 스위치가 최대한 적게 온/오프 하도록 Redundant state를 선택한다. 이를 단상 3-레벨 플라잉 커패시터 인버터에 적용하여 ＰＳＩＭ 시뮬레이션을 통해 유효성을 검증하였다.

• Journal of Power Electronics
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• v.14 no.1
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.