• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.3
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• pp.237-242
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• 2014

Recently much research are has been done into the compositions of lead-free solders. As a result, there has been a rapid increase in the number of new compositions. In the past, the properties of these new compositions were determined and verified through drop-impact tests. However, these drop tests were expensive and it took a long time to obtain a result. The main goal of this study was to establish an analytical method capable of predicting the impact life-time of a new solder composition for board-level flip chips though the application of drop simulations using LS-DYNA. Based on the reaction load obtain with LS-DYNA, the drop-impact fracture cycles were predicted. The study was performed using a Sn-3.0Ag-0.5Cu solder (305 composition). To verify the reliability of the proposed analytical method, the results of the drop-impact tests and life-time analysis were compared, and were found to be in good agreement. Thus, the new analytical method was shown to be very useful and effective.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.2
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• pp.193-201
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• 2011

Recently, mechanical reliabilities including a drop test have been a hot issue. In this paper, solder balls with new components which are Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu-0.05N are introduced, and board level drop test for them are conducted under JEDEC standard in which the board with 15 flip chips is dropped as 1,500g acceleration during 0.5ms. The drop simulations are studied by using a implicit method in the ANSYS LS-DYNA, and modal analysis is made. Through both analyses, the solder balls with new components are evaluated under the drop. It is found that the maximum stress of each chip is occurred between the solder ball and the PCB, and the highest value among the maximum stresses in the chips is occurred on the chip nearest to fixed holes on the board in the drop tests and simulations.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.127-130
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• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.55-56
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• 1998

The 3-D Fast Gradient Echo (Turbo FLASH, Turbo Fast Low Angle Shot) sequence is optimized to achieve a good T1 contrast using variable excitation flip angles. In Turbo FLASH sequence, depending on the contrast preparation scheme, various types of image contrast can be established. While proton density contrast is obtained when using a short repetition time with a short echo time and small flip angles, T1 or T2 weighting can be obtained with proper contrast preparation sequences applied before the above proton density Turbo FLASH sequence. To maximize the contrast to noise ratio while retaining a sharp impulse response (smooth frequency domain response), the excitation flip-angle pattern is optimized through simulation and experiments. The TI (the delay after the preparation sequence which is a 180 degree inversion RF pulse in the IR T1 weighted imaging case), TD (the delay time between the Turbo FLASH sequence and the next preparation), and TR are also optimized fur the best image quality. The proposed 3-D Turbo FLASH provides $1mm\times1mm\times1.5mm$ high resolution images within a reasonable 5-8 minutes of imaging time. The proposed imaging sequence has been implemented in a Medison's Magnum 1.0T system and verified through simulations as well as human volunteer imaging. The experimental results show the utility of the proposed method.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.83-89
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• 2016

Flip-learning enables an effective teaching and learning in accordance with the deepening degree of engineering education as a framework that enables learning according to the individual differences of the theoretical aspects, and solving real problems and practice of the learner-centered education through the application of this. The subject of basic fluid power practice which is used in various industries requiring factory automation aims at understanding of the composition and operating principles of pneumatic components and programming of electric sequential circuits, building the design ability of pneumatic system. This subject goes by 3 hour classes with theory and practice side by side. So it has not enough time to instruct students various contents related in this subject. In this study, the instructional design was performed according to the KOREATECH (Korea University of Technology and Education) flip-learning basic model for the effective teaching of 'Basic Fluid Power Practice' in basic engineering practice courses,. And the effectiveness of flip-learning is analyzed through the students survey after performing classes.

• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.18 no.4
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• pp.362-368
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• 2009

In general, circuit board assemblies experience various mechanical loadings during assembly and in actual use. The repeated cyclic bending can cause electrical failures due to circuit board cracks, solder interconnects cracks, and the component cracks. In this paper, we report on the failure characteristics of semiconductor chips under the repeated cyclic bending. We first describe a new 4-point bending tester, which is developed according to JEDEC standard No. 22B113. The performance of the tester is then estimated through actual experiments. Test results reveal that the cracks first occur on the outer balls around 20,000 cycles and gradually propagate to the inner balls where cracks are found around 70,000 cycles.

• ETRI Journal
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• v.26 no.1
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• pp.1-6
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• 2004

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and ${\sqrt{T}}$-dependent thermal red shifts. We observed uniform bottom emissions from a 1-kb smart pixel chip of a $32{\times}32$ InGaAs PQR laser array flip-chip bonded to a 0.35 ${\mu}m$ CMOS-based PQR laser driver. The PQR-CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.19-25
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• 2011

The size reduction of the semiconductor chip and the improvement of the electrical performance have been enabled through the introduction of the Cu/Low-K process in modern electronic industries. However, Cu/Low-K has a disadvantage of the physical properties that is weaker than materials used for existing semiconductor manufacture process. It causes many problems in chip manufacturing and package processes. Especially, the delamination between the Cu layer and the low-K dielectric layer is a main defect after the temperature cycles. Since the Cu/Low-K layer is located on the top of the pad of the flip chip, the stress on the flip chip affects the Cu/Low-K layer directly. Therefore, it is needed to improve the underfill process or materials. Especially, it becomes very important to select the underfill to decrease the stress at the flip-chip and to protect the solder bump. We have solved the delamination problem in a 90 nm Cu/Low-K flip-chip package after the temperature cycle by selecting an appropriate underfill.