• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.79-89
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• 2014

It has been an increase in consumers who want a high-capacity and fast speed by the newly diffused mobile device(Smart phones, Ultra books, Tablet PC). As a result, the demand for Flash Memory is constantly increasing. Flash Memory is separated by a NAND-type and NOR-type. NAND-type Flash Memory speed is slow, but price is cheaper than the NOR-type Flash Memory. For this reason, NAND-type Flash Memory is widely used in the mobile market. So Fault Detection is very important for Flash Memory Test. In this paper, Proposed PMBIST for Pattern Test of NAND-type Flash Memory improved Fault detection.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.47-58
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• 2005

There are two major type of flash memory products, namely, NAND-type and NOR-type flash memory. NOR-type flash memory is generally deployed as ROM BIOS code storage because if offers Byte I/O and fast read operation. However, NOR-type flash memory is more expensive than NAND-type flash memory in terms of the cost per byte ratio, and hence NAND type flash memory is more widely used as large data storage such as embedded Linux file systems. In this paper, we designed an efficient flash memory file system based an Embedded system and presented to make up for reduced to Swapping a weak System Performance to flash file system using NAND-type flash memory, then proposed Swapping algorithm insured to an Execution time. Based on Implementation and simulation studies, Then, We improved performance bases on NAND-type flash memory to the requirement of the embedded system.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.177-185
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• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.72-82
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• 2014

Recently, the size of semiconductor industry market is constantly growing, due to the increase in diffusion of smart-phone, tablet PC and SSD(Solid State Drive). Also, it is expected that the demand for TLC NAND-type flash memory would gradually increase, with the recent release of TLC NAND-type flash memory in the SSD market. There have been a lot of studies on SLC NAND flash memory, but no research on TLC NAND flash memory has been conducted, yet. Also, a test of NAND-type flash memory is depending on a high-priced external equipment. Therefore, this study aims to suggest a structure for an autonomous test with no high-priced external test device by modifying the existing SLC NAND flash memory and MLC NAND flash memory test algorithms and patterns and applying them to TLC NAND flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.26-33
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• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.13-13
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory and Planar-type SONOS flash memory are analyzed. Compared to the Planar-type SONOS device, Fin-type SONOS device shows a good short channel effect immunity. Moreover, memory characteristics such as PIE speed, Endurance and Retention of FinFET SONOS flash are batter than that of conventional Planar-type SONOS flash memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.235-243
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• 2018

NAND flash memory has been widely used for embedded systems as storage device and the flash memory file systems such as JFFS2, YAFFS/YAFFS2 have been adopted by these embedded systems. The flash memory file systems provide the high performance and overcome the limitations of flash memory. However, these file systems don't solve the slow mount time problem when a sudden power failure happens. In this paper, we proposed a flash memory management method for enhancing the recovery performance. The proposed method manages the flash memory block type and stores the block type information at recovery image block. When file operations are occurred, our method stores the file information at the metadata block before and after the file operation. When mounting the flash memory, our method only scans the recovery image blocks and metadata blocks. The proposed method reduces the mount time by seeking the metadata block locations fast by using the recovery image blocks. We implemented the proposed method and evaluation results show that our method reduces the mount time 13 ~ 46 % compared with YAFFS2.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.129-140
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• 2014

BIST(Built-in self test) is to detect various faults of the existing memory and BIRA(Built-in redundancy analysis) is to repair detected faults by allotting spare. Also, BISR(Built-in self repair) which integrates BIST with BIRA, can enhance the whole memory's yield. However, the previous methods were suggested for RAM and are difficult to diagnose disturbance that is NAND-type flash memory's intrinsic fault when used for the NAND-type flash memory with different characteristics from RAM's memory structure. Therefore, this paper suggests a BISD(Built-in self diagnosis) to detect disturbance occurring in the NAND-type flash memory and to diagnose the location of fault, and BISR to repair faulty blocks.