• Transactions of the Society of Information Storage Systems
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• v.7 no.1
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• pp.7-12
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• 2011

The flash memory has been remarked as the next generation media of portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major data storage components for desktop and servers. The purpose of our study is to upgrade a traditional mirroring scheme based on SSD storages due to the relatively slow or freezing characteristics of write operations, as compared to fast read operations. For this work, we propose a new storage management scheme called Memory Mirror-Switching based on traditional mirroring scheme. Our Mirror-Switching scheme improves flash operation performance by switching write-workloads from flash memory to RAM and delaying write operations to avoid freezing. Our test results show that our scheme significantly reduces the write operation delay and storage freezing.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.6
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• pp.383-391
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• 2011

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.1-8
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• 2011

NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way, victim and fully associative buffer with two or four sizes.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.14-20
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• 2009

Recently, NAND flash memory is used not only for portable devices, but also for personal computers and server computers. Buffer cache replacement policies for the hard disks such as LRU and LFU are not good for NAND flash memories because they do not consider about the characteristics of NAND flash memory. CFLRU and its variants, CFLRU/C, CFLRU/E and DL-CFLRU/E(CFLRUs) are the buffer cache replacement policies considered about the characteristics of NAND flash memories, but their performances are not better than those of LRD. In this paper, we propose a new buffer cache replacement policy for NAND flash memory. Which is based on LFU and is taking into account the characteristics of NAND flash memory. And we estimate the performance of hit ratio and flush operation numbers. The proposed policy shows better hit ratio and the number of flush operation than any other policies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1418-1425
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• 2009

This paper proposes a novel FTL (Flash Translation Layer) algorithm based on sector-level mapping to reduce the number of total erase operations in flash memory accesses. The proposed algorithm can reduce the number of erase operations by utilizing the sector-level mapping table when writing data at flash memory. Sector-level mapping technique reduces flash memory access time and extendsthe life time of the flash memory. In the algorithm, wear-leveling is implemented by selecting victim blocks having the minimal number of erase operations, when empty spaces for write are not available. To evaluate the performance of the proposed FTL algorithm, experiments were performed on several applications, such as MP3 players, MPEG players, web browsers and document editors. The proposed algorithm reduces the number of erase operations by 72.4% and 61.9%, when compared with well-known BAST and FAST algorithms, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.836-840
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• 2009

Many researchers have studied flash memory in order to replace hard disk storages. Many FTL algorithms have been proposed to overcome physical constraints of flash memory such as erase-before-write, wear leveling, and poor write performance. Therefore, these constraints should be considered for testing FTL algorithms and the performance evaluation of flash memory. As doing the experiments, we suffer from several problems with costs and settings in experimental configuration. When we, for example, replay the traces of Oracle to evaluate the I/O performance with flash memory, it is hard to extract exact traces of I/O operations in Oracle. Since there are only write operations in the log, it is impossible to gather read operations. In MySQL and SQLite, we can gather the read operations by changing I/O functions in the source codes. But it is not easy to search for the exact points about I/O and even if we can find out the points, we might get wrong results depending on how we modify source codes to get I/O traces. The FlaSim proposed in this paper removes the difficulties when we evaluate the performance of FTL algorithms and flash memory. Our Linux drivers emulate the flash memory as a hard disk. And we can easily obtain the usage statistics of flash memory such as the number of write, read, and erase operations. The FlaSim can be gracefully extended to support the additional modules implemented by novel algorithms and ideas. In this paper, we describe the structure of FTL emulator, development tools and operating methods. We expect this emulator to be helpful for many experiments and research with flash memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.103-108
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• 2014

The flash memory which is exploited on hand-held devices such as smart phones is a non-volatile storage and has the benefit that it can store mass data at a small sized chip. To process queries on the mass data stored in the flash memory, the index scheme should be exploited. However, since the write operation of the flash memory is slower than the read operation and the overwrite is not supported, it is required to reevaluate the performance of the index and find out the drawbacks. In this paper, we evaluate the performance of a space division typed index scheme on the flash memory. To do this, we implement the fixed grid file and measure the average speeds of the query and update processing on a various condition and compare the value of the flash memory with that of the magnetic disk.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.761-767
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• 2010

In the case of NAND flash memory, a whole block needs to be erased for update operations because update-in- place operations are not supported in NAND flash memory. Blocks of NAND flash memory have the limited erasure cycles, so frequently updated data (hot data) easily makes blocks worn out. As the result, the capacity of NAND flash memory will be reduced by hot data. In this paper, we propose a wear-leveling algorithm by discriminating hot and cold data based on the update patterns of data. When we applied this scheme to NAND flash memory, we confirmed that the erase counts of blocks became more uniform by mapping hot data to a block with a low erase count and cold data to block with a high erase count.

• Journal of KIISE:Databases
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• v.36 no.1
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• pp.1-7
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• 2009

Flash memory has its unique characteristics: i.e., (1) the write operation is much more costly than the read operation. (2) In-place updating is not allowed. In this paper, we first analyze how these characteristics affect the performance of record management in flash memory, and discuss the problems with previous methods for record management when they are applied to flash memory environment. Next, we propose a new record management method to be suitable for flash memory environment. The proposed method employs a new concept of a container that makes it possible to overwrite data on flash memory several times when performing insertions, deletions, and modifications of records. As a result, this method reduces the number of overwrite operations, and consequently does the number of erase operations. The results of experiments show that our method improves the performance by up to 34%, compared with the previous one.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.325-334
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• 2008

Flash memory is widely used as a storage medium for mobile devices such as cell phones, MP3 players, PDA's due to its tiny size, low power consumption and shock resistant characteristics. Additionally, some computer manufacturers try to replace hard-disk drives used in Laptops or personal computers with flash memory. More recently, there are some literatures on developing a flash memory-aware $B^+$-tree index for an efficient key-based search in the flash memory storage system. They focus on minimizing the number of "overwrites" resulting from inserting or deleting a sequence of key values to/from the $B^+$-tree. However, in addition to this factor, the size of a physical page allocated to a node can affect the maintenance cost of the $B^+$-tree. In this paper, with diverse experiments, we compare and analyze the costs of construction and search of the $B^+$-tree and the space requirement on flash memory as the node size increases. We also provide sorting-based or non-sorting-based algorithms to be used when inserting a key value into the node and suggest an header structure of the index node for searching a given key inside it efficiently.