• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.8
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• pp.578-584
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• 2004

The CSVM(Current Support Vector Machine) that is a digital architecture performing all phases of recognition process including kernel computing, learning, and recall of SVM(Support Vector Machine) on a chip is proposed. Concurrent operation by parallel architecture of elements generates high speed and throughput. The classification problems of bio data having high dimension are solved fast and easily using the CSVM. Quadratic programming in original SVM learning algorithm is not suitable for hardware implementation, due to its complexity and large memory consumption. Hardware-friendly SVM learning algorithms, kernel adatron and kernel perceptron, are embedded on a chip. Experiments on fixed-point algorithm having quantization error are performed and their results are compared with floating-point algorithm. CSVM implemented on FPGA chip generates fast and accurate results on high dimensional cancer data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.745-747
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• 2014

본 논문에서는 OFDM 기반 무선 백홀 시스템에 적용 할 수 있는 채널 추정 및 $2{\times}2$ MIMO 알고리즘을 VHDL로 구현하여, 무선 백홀 시스템용으로 제작한 보드의 FPGA에서 신호 검출 성능을 검증한다. 이를 위해, 먼저 매틀랩(Matlab) simulink를 이용하여 채널 추정 및 $2{\times}2$ MIMO 알고리즘을 floating-point와 fixed-point 모델로 설계하여 성능을 검증하고, 그 다음 Modelsim을 이용하여 VHDL로 구현한다. 구현된 알고리즘의 성능 검증을 위해 설계한 simulink 모델, Modelsim 시뮬레이션, ISE Chipscope, 그리고 오실로스코프로 측정한 결과들을 비교한다. 비교결과, Modelsim 시뮬레이션, ISE Chipscope, 그리고 오실로스코프로 측정한 결과들이 서로 동일함을 확인하였으며, simulink 모델의 결과와는 약간의 오차를 보임을 확인하였다.

• Advances in aircraft and spacecraft science
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• v.6 no.5
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• pp.371-389
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• 2019

The implementation of a robust $H_{\infty}$ Control, which is numerically efficient for uncertain nonlinear dynamics, on longitudinal and lateral autopilots is realised for a quarter scale Piper J3-Cub model accepted as an unmanned aerial vehicle (UAV) under the condition of sensor noise and disturbance effects. The stability and control coefficients of the UAV are evaluated through XFLR5 software, which utilises a vortex lattice method at a predefined flight condition. After that, the longitudinal trim point is computed, and the linearization process is performed at this trim point. The "${\mu}$-Synthesis"-based robust $H_{\infty}$ control algorithm for roll, pitch and yaw displacement autopilots are developed for both longitudinal and lateral linearised nonlinear dynamics. Controller performances, closed-loop frequency responses, nominal and perturbed system responses are obtained under the conditions of disturbance and sensor noise. The simulation results indicate that the proposed control scheme achieves robust performance and guarantees stability under exogenous disturbance and measurement noise effects and model uncertainty.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.7-14
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• 2003

MPEG-1 audio standard is the algorithm for the compression of high-qualify digital audio signals. The standard dictates the functions of encoder and decoder pair, and includes three different layers as the complexity and the performance of the encoder and decoder. In this paper, we implemented the real-time system of MPEG-1 audio layer III decoder(MP3) with the TMS320C541 fixed point DSP chip. MP3 algorithm uses psycho-acoustic characteristic of human hearing system, and it reduces the amount of data with eliminating the signals hard to be heard to the hearing system of human being. It is difficult to implement MP3 decoder with fixed Point DSP because of it's broad dynamic range. We implemented realtime system with fixed DSP chip by using weighted look-up tables to reduce the amount of calculation and solve the problem of broad dynamic range.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.10
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• pp.1059-1066
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• 2011

This paper makes a close inquiry into ill-conditioning that may be occurred in wireless localization of the sensor nodes based on network signals in the wireless sensor network and provides the clue for solving the problem. In order to estimate the location of a node based on the range information calculated using the signal propagation time, LS (Least Squares) method is usually used. The LS method estimates the solution that makes the squared estimation error minimal. When a nonlinear function is used for the wireless localization, ILS (Iterative Least Squares) method is used. The ILS method process the LS method iteratively after linearizing the nonlinear function at the initial nominal point. This method, however, has a problem that the final solution may converge into a LM (Local Minimum) instead of a GM (Global Minimum) according to the deployment of the fixed nodes and the initial nominal point. The conditions that cause the problem are explained and an adaptive method is presented to solve it, in this paper. It can be expected that the stable location solution can be provided in implementation of the wireless localization methods based on the results of this paper.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.9
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• pp.759-765
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• 2016

This paper presents the principle, dynamics modeling and control, hardware implementation, and flight test result of a hybrid-type unmanned aerial vehicle (UAV). The proposed UAV was designed to provide both hovering and fixed-wing type aerodynamic flight modes. The UAV's flight mode transition was achieved through the attitude transformation in pitch axis, which avoids a complex rotor tilt mechanism from a structural and control viewpoint. To achieve this, a different navigation coordinate was introduced that avoids the gimbal lock in pitch singularity point. Attitude and guidance control algorithms were developed for the flight control system. For flight test purposes, a quadrotor attached with a tailless fixed-wing structure was manufactured. An onboard flight control computer was designed to realize the navigation and control algorithms and the UAV's performance was verified through the outdoor flight tests.

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.78-83
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• 2000

Vocoders used in digital mobile phone adopt new improved algorithm to achieve better communication quality. Therefore the communication problem occurs between mobile phones using different vocoder algorithms. In this paper, the efficient implementation of 8kbps and 13kbps QCELP into one DSP chip to solve this problem is presented. We also describe the optimization method at each level, that is, algorithm-level, equation-level, and coding-level, to reduce the complexity for the QCELP vocoder algorithm implementation. The complexity in the codebook search-loop that is the main part for the QCELP algorithm complexity can be reduced about 50% by using these optimizations. The QCELP implementation with our DSP requires only 25 MIPS of computation for the 8kbps and 33 MIPS for the 13kbps ones. The DSP for our real-time implementation is a 16-bit fixed-point one specifically designed for vocoder applications and has a simple architecture compared to general-purpose ones in order to reduce the power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.713-720
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• 2012

Recently, holography has received much attention as the next generation visual technology. Hologram is obtained by the optical capturing, but in recent years it is mainly produced by the method using computer. This method is named by computer generated hologram (CGH). Since CGH requires huge computational amount, if it is implemented by S/W it can't work in real time. Therefore it should use FPGA or GPU for real time operation. If it is implemented in the type of H/W, it can't obtain the same quality as S/W due to the bit limitation of the internal system. In this paper, we analyze the bit width for minimizing the degradation of the hologram and reducing more hardware resources and propose guidelines for H/W implementation of CGH. To do this, we performs fixed-points simulations according to main internal variables and arithmetics, analyze the numerical and visual results, and present the optimal bit width according to application fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.