• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.6
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• pp.1383-1388
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• 2013

Even though a dual lens stereoscopic camera allows for convenient stereoscopic photography, the necessity for the research comes up, since the dual lens stereoscopic camera can cause visual discomfort during zoom-in due to the fixed convergence point. We propose a method based on which a convergence point can be adjusted to prevent visual discomfort during zoom-in for a dual lens stereoscopic camera. First, the relational model is classified into nine kinds and defined, depending on locations of focus, object, and convergence point. And then, the method to minimize visual discomfort is suggested by adjusting convergence point on the given model. We also implement the suggested methods with anaglyph computer graphic and demonstrate the superiority of them.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.456-459
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• 2013

Even though a dual lens stereoscopic camera allows for convenient stereoscopic photography, the necessity for the research comes up, since the dual lens stereoscopic camera can cause visual discomfort during zoom-in due to the fixed convergence point. We propose a method based on which a convergence point can be adjusted to prevent visual discomfort during zoom-in for a dual lens stereoscopic camera. First, the relational model is classified into nine kinds and defined, depending on locations of focus, object, and convergence point. And then, the method to minimize visual discomfort is suggested by adjusting convergence point on the given model. We also implement the suggested methods with anaglyph computer graphic and demonstrate the superiority of them.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.85-100
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• 1991

In the discussion of digital mobile communication systems the speech coder based on the high quality low bit rate is an essential part of topics to overcome the limited availability of radio spectrum, which will enhance the communication services. In this paper we present the implementation and performance evaluation of 13kbps RPE LTP speech coder. An implementation of a real time full duplex coder with 75% of DSP loading rate using a single DSP chip has been shown, and also the fixed point simulations for H/W implementation has been performed. Finally, analysis result for relative bit importance of each transmitting parameter has been shown for channel coding.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.3
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• pp.259-265
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• 2012

This paper introduces a method for design and implementation of a current controller for boost converter operating in continuous conduction mode (CCM) using a digital signal processor (DSP). A Proportional-Integral (PI) type current controller outputs an average voltage command for inductor, used in the input side of the boost converter, and the duty-ratio of PWM (pulse width modulation) signal for switching device is directly calculated from the average voltage command. The gains of the PI current controller are selected such that the current response characteristics are the same as those of a first-order low-pass filter. The proposed current control scheme is implemented using a DSP based on fixed-point math operations and an experimental study has been performed to validate the proposed method.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.533-536
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• 1999

We consider digital implementation problems of continuous-time controllers. In general, digital controllers use fixed point representation of number and of finite word length(FWL). Under these conditions, this paper investigates the closed-loop stability caused by three design constraints; (i) finite precision representation of the controller parameters, (ii) realization forms such as direct form, cascade form, and parallel form, and (iii) sampling time. We calculate the coefficient stability margins of both predesigned controllers and controller to be implemented. This method can be applied to determine the word length, realization structure, and sampling time so that remains the stability.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.96-102
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• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1412-1420
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• 1999

In order to enhance multi-channel audio signals, Dolby Pro Logic is widely used especially for the Hi-Fi audio system, since it can provide highly stereophonic effects and a nice separation of multi-channel sound. This paper describes an implementation of Dolby Pro Logic decoder with ARM-7 core. The code is modified for the fixed point operation and optimized. For the verification of the code, the operation time and the precision are estimated thoroughly. As a result, it is verified that Dolby Pro Logic decoder can be implemented with ARM-7 core operating at 54 MHz.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.591-595
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• 2011

In this paper, we design the hardware architecture of the BICM(Bit Interleaved Coded Modulation) module for next generation European broadcast system and implement the BICM module with DSP(Digital Signal Processor) TMS320C6474. Simulation result shows that the BER(Bit Error Rate) performance of the fixed-point BICM module using more than 8 bits is very similar to that of the floating-point BICM module.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.167-170
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• 2002

In this paper, we implement a 2.4 kbps STC speech codec using the TMS320C6201 DSP The main job for this work is twofold: one is to convert floating-point operation in the codec into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real time with memory size as small as possible. The implemented decoder uses 54.8 kbyte of program memory, 29.7 kbyte of data ROM and 55.2 kbyte of data RAM, respectively. It also uses about 45% of maximum computation capacity of TMS320C6201.