• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.59-70
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• 2007

In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

• International Journal of Contents
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• v.15 no.1
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• pp.52-57
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• 2019

The purpose of this research is to evaluate teachers' perception of Korean's achievement standard-based testing system (ASTS) and its process of implementation, and to propose a method of evaluating students' academic aptitude based on university entrance examinations. The core of the 2015 Revised National Curriculum is asserted by changes in classroom instruction, specifically encouraging students' participation in class based on a new method to evaluate student achievement. A total of 124 teachers in charge of student career counseling in middle and high schools in the Jeonbuk province participated in the study. The schools implementing the new method of ASTS were using 61.6% for unit school cut-off point, as opposed to the existing fixed cut-off point of 38.4%. The teachers understanding of the achievement evaluation method was rated 3.54 on the 5-point Likert scale, implying that they had a relatively good understanding of the method. Some of the challenges associated with reflecting the scores from the new student ASTS include difficulty of comparing scores across schools; grade inflation; advantages and disadvantages associated with the type of high school; and the increased importance of university entrance examination. In the ASTS, the fairness during the evaluation of the high school grades and the consequently the reliability of the evaluation prove worrying. As an ultimate result, selecting students based on university admissions data became untrustworthy. There should be further discussions on how students' achievement obtained from the new ASTS should be applied during the university admission process and how students' academic aptitude can be assessed in order to set a direction for secondary school education.

• Smart Media Journal
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• v.4 no.4
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• pp.111-119
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• 2015

As a variety of HMD(Head Mounted Display) has come out, the production of 3D images onto which VR(Virtual Reality) technologies are grafted has been contributed to activating the production of image contents depending on a tangible or immersing type. VR-based image contents have enlarged their applicability across the entertainment industry from animation and game to realistic images. At the same time, the solution development for producing VR image contents has also gained elasticity. However, among those production solutions which have been used until now, fixed stereo camera based photographing has a limit that the binocular disparity of a user is fixed. This does not only restrict a way of expression a producer intends to direct, but also may cause the effect of 3D or space not to be sensed enough as view condition is not considered enough in a user's side. This study is aimed at resolving with skills applying in the latter part of 3D image production the problem that convergence points may be adjusted with restriction, which tends to happen at the time of the production of VR image contents. The later stage of the 3D imaging work analyzes and applies to game engines the significance of adjusting convergence points through the visualization of binocular disparity so that it is available to implement a function that the points could be controlled at random by a user.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.11
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• pp.1447-1454
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• 2018

In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.371-373
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• 2015

This paper describes an analysis of hardware design conditions of moving object detection algorithm which is based on effective Gaussian mixture learning (EGML). The simulation model of EGML algorithm is implemented using OpenCV, and it is analyzed that the effects of parameter values on background learning time and moving object detection sensitivity for various images. In addition, optimal design conditions for hardware implementation of EGML-based MOD algorithm are extracted from fixed-point simulations for various bit-width parameters.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.78-86
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• 1998

This paper presents a numerical method of the minimum-time trajectory planning for a robot manipulator amid obstacles. Each joint displacement is represented by the linear combination of the finite-term quintic B-splines which are the known functions of the path parameter. The time is represented by the linear function of the same path parameter. Since the geometric path is not fixed and the time is linear to the path parameter, the coefficients of the splines and the time-scale factor span a finite-dimensional vector space, a point in which uniquely represents the manipulator motion. The displacement, the velocity and the acceleration conditions at the starting and the goal positions are transformed into the linear equality constraints on the coefficients of the splines, which reduce the dimension of the vector space. The optimization is performed in the reduced vector space using nonlinear programming. The total moving time is the main performance index which should be minimized. The constraints on the actuator forces and that of the obstacle-avoidance, together with sufficiently large weighting coefficients, are included in the augmented performance index. In the numerical implementation, the minimum-time motion is obtained for a planar 3-1ink manipulator amid several rectangular obstacles without simplifying any dynamic or geometric models.

• The Journal of the Acoustical Society of Korea
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• v.15 no.2
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• pp.12-20
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• 1996

A real-time Dolby AC-3 decoder has been implemented using a 20-bit fixed point general purpose DSP chip. It is shown that AC-3 decoder of this paper has same performance as decoder of C-simulator on PC. And also, it is applied to DVD player. Especially, in this paper, we proved that it has shorter latency time than that of previous AC-3 decoder.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.279-282
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• 2012

In this paper, a hardware architecture of phase calculator for 3D image processing is proposed. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. Phase calculator designed in Verilog HDL is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification.

• Korean Institute of Interior Design Journal
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• v.22 no.6
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• pp.190-198
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• 2013

With globalization and the execution of a self-governing system, the government-oriented system has been transformed into a city-oriented system. The importance of the competitive power of a city is thus increasing. Because of this each region is trying to develop its own differentiated image and to create branding using unique historical and cultural resources and, as one of the strategies for this, public spaces have been developed. For a public space to be used as a means to promote the attractiveness of a city, creates a local image and works as a medium to help a community of people realize a pleasant life. Therefore, in this study, I am clarified theoretically the meaning of placeness and form factors. and study realization methods in the space around the public space case. The results of the study are as following. In the modern space, Place is to be understood as a recognition and experience. Therefore rather than spatial structure physical fixed, recognition through the human experience is an important feature of the place-making, it is necessary to access in spatial planning based on this point of view. The factors of the placeness formation are physical environment factors, activity elements of the human, the meaning factors. and these elements form the placeness through via interaction. Therefore, even space implementation of the place, it is necessary to grasp the elements of each, as well as the physical aspects in particular, planning programmatic and various functions must be parallel strategically. There is a need to implement a space device that can be carried out in space activities.