• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.259-259
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• 2000

In the recent, the size of hardware is smaller and the structure is simpler, without reducing the performance of the digital controller. Accordingly, the fixed-point arithmetic is very important in the digital controller. This paper presents simulation to apply the robust control algorithms to DVDR servo controller using the floating-point and fixed-point arithmetic from the matlab. Also, it analyses and compares the performance of control algorithms in the each of point calculation and presents a method for improvement of drop in the performance, quantization error and overflow/underflow from using the fixed-point arithmetic

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.250-253
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• 2000

In this paper, we Implement a new arithmetic computation for MPEG audio data to overcome the limitations of real number processing in the fixed-point arithmetics, such as: overheads in processing time and power consumption. We aims at efficiently dealing with real numbers by extending the fixed-point arithmetic manipulation for floating-point numbers in MPEG audio data, and implementing the DSP libraries to support the manipulation and computation of real numbers with the fixed-point resources.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• East Asian mathematical journal
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• v.35 no.1
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• pp.59-66
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• 2019

In this paper we study implicit-explicit (IMEX) methods combined with a semi-Lagrangian scheme to evaluate the prices of fixed strike arithmetic Asian options under jump-diffusion models. An Asian option is described by a two-dimensional partial integro-differential equation (PIDE) that has no diffusion term in the arithmetic average direction. The IMEX methods with the semi-Lagrangian scheme to solve the PIDE are discretized along characteristic curves and performed without any fixed point iteration techniques at each time step. We implement numerical simulations for the prices of a European fixed strike arithmetic Asian put option under the Merton model to demonstrate the second-order convergence rate.

• Journal of IKEEE
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• v.22 no.3
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• pp.805-809
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• 2018

In this paper, we analyze the change of accuracy when fixed point arithmetic is used instead of floating point arithmetic in binary weight network(BWN). We observed the change of accuracy by varying total bit size and fraction bit size. If the integer part is not changed after fixed point approximation, there is no significant decrease in accuracy compared to the floating-point operation. When overflow occurs in the integer part, the approximation to the maximum or minimum of the fixed point representation minimizes the decrease in accuracy. The results of this paper can be applied to the minimization of memory and hardware resource requirement in the implementation of FPGA-based BWN accelerator.

• The KIPS Transactions:PartB
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• v.13B no.4 s.107
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• pp.429-438
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• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.49-52
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• 2010

디지털 신호처리 알고리즘들은 실제 시스템에 적용할 때 임베디드 시스템 등 하드웨어의 성능과 소비전력 및 비용에 제약이 있을 경우 연산 정밀도가 높은 floating-point 연산 대신 제한된 정밀도와 적은 연산 비용을 요구하는 fixed-point 연산을 사용하여 구현한다. 시스템의 개발단계에서는 적용할 알고리즘을 floating-point 연산을 이용한 코드를 먼저 작성한 후 이를 fixed-point 연산으로 대체하는 과정을 거치게 되는데, 이는 숙련된 개발자와 상당한 양의 개발기간을 요하는 까다로운 작업이다. 이에 본 연구에는 코드작성 편의를 높이고 개발기간을 단축하기 위해 C++ template 기반의 fixed-point 연산 라이브러리를 개발하였다. 이는 floating-point 연산 코드와 fixed-point 연산 코드를 별도로 개발할 필요 없이 하나의 코드를 이용하여 자유로이 연산 정밀도를 지정할 수 있으며 개발자는 기존의 floating-point 연산을 이용하는 코드를 작성하는 것처럼 쉽게 코드를 작성할 수 있도록 한다. 또한, template 기반으로 작성되어 기존의 연구들과 달리 추가적인 작업도구 없이도 범용 C++ 컴파일러가 최적화된 코드를 생성할 수 있도록 되어있는 것이 특징이다.

• Speech Sciences
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• v.3
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• pp.177-186
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• 1998

This paper describes the procedure of implementing a real-time speech codec, G.723.1 which was developed by DSP Group and standardized by ITU-T, using fixed-point DSP, ADSP-2181. This codec has two bit rates associated with it, 5.3 and 6.3 kbit/s. We implemented only one bit rate, 6.3 kbit/s, of the two with fixed-point 32-bit precision. According to the result of the experiment, the amount of computational burden is about 55 MIPS and its quality is similar to the result of the PC simulation with floating-point arithmetic. In this paper, we proposed a method to use a fixed-point DSP and a procedure for developing a real-time speech codec using DSPs and finally developed a G.723.l speech codec for ADSP-2181.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.677-690
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• 1995

In this paper, we propose the high efficiency data compression capable of error control using block-sorting, move to front(MTF) and arithmetic code with variable length in to fixed out. First, the substring with is parsed into length N is shifted one by one symbol. The cyclic shifted rows are sorted in lexicographical order. Second, the MTF technique is applied to get the reference of locality in the sorted substring. Then the preprocessed sequence is coded using VF(variable to fixed) arithmetic code which can be limited the error propagation in one codeword. The key point is how to split the fixed length codeword in proportion to symbol probabilities in VF arithmetic code. We develop the new VF arithmetic coding that split completely the codeword set for arbitrary source alphabet. In addition to, an extended representation for symbol probability is designed by using recursive Gray conversion. The performance of proposed method is compared with other well-known source coding methods with respect to entropy, compression ratio and coding times.