• 한국통신학회논문지
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• 제21권10호
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• pp.2541-2551
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• 1996

인간의 시각체계는 영상의 밝기의 정도가 균일한 연에서는 잡음에 민감하지만, 변화하는 부분에서는 에지(edge)의 정도가 심할수록 잡음에 둔감하고, 에지부분에서 멀어질수록 잡음에 대한 민감도가 급격하게 증가한다. 이러한 인간의 시각 특성에 기반을 둔 여러가지 영상복원 방식이 제안되고 있는데, 본 논문에서는 영상을 복원함에 있어서 윤곽 부분에서는 변화하는 부분의 선명도를 높이고, 영상이 평탄한 부분에서는 잡음 성분을 많이 억제 시켜서 영상을 주관적으로 향상시키는 적응적 영상복원 방식을 소개한다. 이 방법은 에지 검출을 하기 위해서 각 화소를 기준으로 지역 분산값(local variance)을 사용하여 시각 함수(visibility function)를 구하고, 이 값에 따라 정규화 매개변수를 변환시켜 적응적으로 영상을 복원한다. 즉 영상을 평탄한 부분에서 에지부분까지 몇 단계로 나누어서 각각의 단계에 해당하는 유한 임펄스 CLS 필터를 구현해서 영상을 복원한다.

• ETRI Journal
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• 제33권5호
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 유기절연재료 방전 플라즈마
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• pp.5-12
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• 2000

본 연구에서, Daubechies'Mother Wavelet를 이용한 이산 웨이블렛 변환(Discrete Wavelet Transform)에 기초한 새롭고 효과적인 특정추출방법을 제안하였다. 특정추출을 이용하여 응용방향을 설명하고 또는 통계적 파라메터의 평가를 행하였다. 본 연구에서는 다음과 같은 몇 가지 사실을 알 수 있었다. 1. 시스템에서 발생된 (인가전압이 0[V]) 노이즈라 볼 수 가있는 렌덤노이즈(Random Noise)를 디지털필터인 FIR(Finite Impulse Response)필터를 통하여 상당한 노이즈를 억제할 수가 있었다. 2. 이산 웨이블렛 변환 시 레벨 1~4까지 변환한 결과 최적의 변환상태 Level-3을 기준으로 하였다. 3. 특정추출 파라메터는 음향방출신호의 최대값, 평균값, 분산, 왜도, 첨쇄도를 특정추출파라메터로 이용하였다. 4. 특정추출 결과를 이용하여 전체 열화시간 중 대표적 음향방출신호 중 초기열화신호, 중기열화신호, 말기열화신호를 얻을 수 있었다. 이런 특정추출을 통하여 변압기열화상태를 진단할 수 있는 가능성을 확인 할 수가 있었다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2018년도 추계학술발표대회
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• pp.438-441
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• 2018

In this paper, we propose a finite impulse response (FIR) filter under malicious cyber attacks. The FIR filter shows the robust performance against the malicious cyber attacks. The Kalman filter (KF), one of the widely used filters, is introduced as a comparison of robust performance of the proposed method. The robust performance of the proposed method under malicious cyber attacks is demonstrated through experimental results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.585-591
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• 2000

The wavelet transform is the most recent technique for processing signals with time-varying spectra. In this paper, the wavelet transform is utilized to improved the assessment and multi-resolution analysis of acoustic emission signals generating in partial discharge. This paper especially deals with the assessment of process statistical parameter using the features extracted from the wavelet coefficients of measured acoustic emission signals in case of applied voltage 20[kv]. Since the parameter assessment using all wavelet coefficients will often turn out leads to inefficient or inaccurate results, we selected that level-3 stage of multi decomposition in discrete wavelet transform. We applied FIR(Finite Impulse Response)digital filter algorithm in discrete to suppression for random noise. The white noise be included high frequency component denoised as decomposition of discrete wavelet transform level-3. We make use of the feature extraction parameter namely, maximum value of acoustic emission signal, average value, dispersion, skewness, kurtosis, etc. The effectiveness of this new method has been verified on ability a diagnosis transformer go through feature extraction in stage of acting(the early period, the last period) .

• 융복합기술연구소 논문집
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• 제7권2호
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• pp.25-30
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• 2017

This paper presents the effects of a virtual mass with a low-pass filter on the stability boundary of a virtual spring in the haptic system. In general, a haptic system consists of a haptic device, a sampler, a virtual impedance model and zero-order-hold. The virtual impedance is modeled as a virtual spring and a virtual mass. However the high-frequency noise due to the sampling time and the quantization error of sampled data may be generated when an acceleration is measured to compute the inertia force of the virtual mass. So a low-pass filter is needed to prevent the unstable behavior due to the high-frequency noise. A finite impulse response (FIR) filter is added to the measurement process of the acceleration and the effects on the haptic stability are simulated. According to the virtual mass with the FIR filter and the sampling time, the stability boundary of the virtual spring is analyzed through the simulation. The maximum available stiffness to guarantee the stable behavior is reduced, but simulation results still show that the stability boundary of the haptic system with the virtual mass is larger than that of the haptic system without the virtual mass.

• 한국컴퓨터정보학회논문지
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• 제17권2호
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• pp.113-118
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• 2012

본 연구에서는 IEEE 802.11 OFDM 수신기에 적용하기 위한 DDC(Digital Down Converter) 설계 방법에 대하여 연구하였다. 상용화 칩으로는 구현이 어려운 WiFi 응용서비스의 요구사항을 만족하기 위해서는 적절한 수신기 개발이 필요하다. OFDM 수신기에서 DDC는 AD 컨버터로부터 업 샘플링된 I/Q(Inphase/Quadrature) 신호를 수신하여 decimation을 위한 신호를 만들기 위해 CIC(Cascaded Integrator Comb) 필터블럭을 거쳐 다운 샘플링한 후 다시 이 신호를 보정하기 위한 FIR(Finite Impulse Response) 필터를 거쳐 출력하는 구조이다. 본 연구에서는 WLAN 규격에 적합한 DDC의 구조 및 설계방법 그리고 설계된 결과물의 시뮬레이션 결과에 대하여 분석하였다.

• 한국군사과학기술학회지
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• 제24권5호
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• pp.475-481
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• 2021

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.

• Journal of Information Processing Systems
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• 제15권2호
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.