• Journal of IKEEE
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• v.24 no.1
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• pp.208-215
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• 2020

In this study, the output 380V direct current DC-DC converter for low-voltage direct current(LVDC) distribution was designed in three types, and the voltage and current characteristics of the three types of DC-DC converter were compared and analyzed through simulation. When the converter was configured using a parallel structure with the power metal-oxide semiconductor field-effect transistor and two current suppression insulated-gate bipolar transistors(IGBTs), the time when the output voltage was stabilized at DC 380V was relatively short with 9ms and the range of output current changes was also between 44.8A and 50.2A, indicating that the width of change was much smaller and the effect of current suppression was greater compared to when IGBT was not applied(68~83A). These results suggest that the proposed DC-DC converter for LVDC distribution is likely to be applied to smart grid construction.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.37-43
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• 2009

Silicon dioxide as gate dielectrics was grown at $400^{\circ}C$ on a polycrystalline Si substrate by inductively coupled plasma oxidation using a mixture of $O_2$ and $N_2O$ to improve the performance of polycrystalline Si thin film transistors. In conventional high-temperature $N_2O$ annealing, nitrogen can be supplied to the $Si/SiO_2$ interface because a NO molecule can diffuse through the oxide. However, it was found that nitrogen cannot be supplied to the Si/$SiO_2$ interface by plasma oxidation as the $N_2O$ molecule is broken in the plasma and because a dense Si-N bond is formed at the $SiO_2$ surface, preventing further diffusion of nitrogen into the oxide. Nitrogen was added to the $Si/SiO_2$ interface by the plasma oxidation of mixtures of $O_2/N_2O$ gas, leading to an enhancement of the field effect mobility of polycrystalline Si TFTs due to the reduction in the number of trap densities at the interface and at the Si grain boundaries due to nitrogen passivation.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Composites Research
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• v.36 no.5
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• pp.342-348
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• 2023

There has been increasing demand for real-time monitoring of body and ambient temperatures using wearable devices. Graphene-based thermistors have been developed for high-performance flexible temperature sensors. In this study, the temperature coefficient of resistance (TCR) of monolayer graphene was controlled by coating polyethylenimine (PEI) on graphene surfaces to enhance its temperature-sensing performances. Monolayer graphene grown by chemical vapor deposition (CVD) was wet-transferred onto a target substrate. To facilitate the interfacial doping by PEI, the hydrophobic graphene surface was altered to be hydrophilic by oxygen plasma treatments while minimizing defect generation. The effect of PEI doping on graphene was confirmed using a back-gated field-effect transistor (FET). The CVD-grown monolayer graphene coated with PEI exhibited an improved TCR of -0.49(±0.03) %/K in a temperature range of 30~50℃.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.133-133
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• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• New Physics: Sae Mulli
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• v.68 no.11
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• pp.1192-1195
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• 2018

We studied the electrical properties of organic thin-film transistors (OTFTs) fabricated at different deposition rates by measuring the field-effect mobility and the threshold voltages. As the active layer, pentacene thin film with a thickness of 50 nm was deposited at a rate of $0.05{\AA}/s$ to $1.14{\AA}/s$. The thickness of the drain-source gold electrode was 50 nm. The mobility was $1.9{\times}10^{-1}cm^2/V{\cdot}s$ at a deposition rate of $0.05{\AA}/s$, the mobility increased to $5.2{\times}10^{-1}cm^2/V{\cdot}s$ when the deposition rate was increased to $0.4{\AA}/s$, and then the mobility decreased to $6.5{\times}10^{-1}cm^2/V{\cdot}s$ when the deposition rate decreased to $1.14{\AA}/s$. Thus, the mobility of pentacene OTFTs was observed to depend on the thermal deposition rate.

• The Journal of Korean Society for Radiation Therapy
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• v.27 no.2
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• pp.107-113
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• 2015

Purpose : The measurement of skin dose is very important that treatment of breast cancer. On account of the cold or hot dose as compared with prescription dose, it is necessary to analyse the skin dose occurring during the various plan of the breast cancer treatment. At our hospital, we want to apply various analyses using a diversity of dosimeters to the breast cancer treatment. Subjectss and Methods : In the study, the anthropomorphic phantom is used to find out the dose difference of the skin(draining site), scar and others occurring from the tangential treatment plan of breast cancer. We took computed tomography scan of the anthropomorphic phantom and made plans for the treatment planing using open and wedge, Field-in-Field, Dose fluence. Using these, we made a comparative analysis of the dose date points by using the Eclipse. For the dose comparison, we place the anthropomorphic phantom in the treatment room and compared the measurement results by using the TLD and MOSFET on the dose data points. Results : On the central point of treatment planing basis, the upward and downward skin dose measured by the MOSFET was the highest when the fluence was used. The skin dose of inner and outer was distinguished from the figure(5.7% ~ 10.3%) when the measurements were fulfilled by using TLD and MOSFET. The other side of breast dose was the lowest in the open beam, on the other hand, is highest in the Dose fluence plan. In the different kinds of treatment, the dose deviation of inner and outer was the highest, and so this was the same with the TLD and MOSFET measurement case. The outer deviation was highest in the TLD, and the Inner'was highest in the MOSFET. Conclusion : Skin dose in relation to the treatment plan was the highest in the planing using the fluence technique in general and it was supposed that the high dose had been caused by the movement of the MLC. There's some differences among the all the treatment planning, but the sites such as IM node occurring the lack of dose, scar, drain site are needed pay close attention. Using the treatment planning of dose fluence is good to compensate the lack of dose, but It increases the dose of the selective range rather than the overall dose. Therefore, choosing the radiotherapy technique is desirable in the lights of the age and performance of the patient.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.679-682
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• 2005

Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.1
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• pp.37-44
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• 2015

In this paper, we have investigated a selective assembly method of single-walled carbon nanotubes (SWCNTs) on a silicon substrate using only photolithographic process and then proposed a fabrication method of field effect transistors (FETs) using SWCNT-based patterns. The aminopropylethoxysilane (APTES) patterns, which are formed for positively charged surface molecular patterns, are utilized to assemble and align millions of SWCNTs and we can more effectively assemble on a silicon (Si) surface using this method than assembly processes using only the 1-octadecyltrichlorosilane (OTS). We investigated a selective assembly method of SWCNTs on a Si surface using surface-programmed APTES and OTS patterns and then a fabrication method of FETs. photoresist(PR) patterns were made using photolithographic process on the silicon dioxide (SiO2) grown Si substrate and the substrate was placed in the OTS solution (1:500 v/v in anhydrous hexane) to cover the bare SiO2 regions. After removing the PR, the substrate was placed in APTES solution to backfill the remaining SiO2 area. This surface-programmed substrate was placed into a SWCNT solution dispersed in dichlorobenzene. SWCNTs were attracted toward the positively charged molecular regions, and aligned along the APTES patterns. On the contrary, SWCNT were not assembled on the OTS patterns. In this process, positively charged surface molecular patterns are utilized to direct the assembly of negatively charged SWCNT on SiO2. As a result, the selectively assembled SWCNT channels can be obtained between two electrodes(source and drain electrodes). Finally, we can successfully fabricate SWCNT-based multi-channel FETs by using our self-assembled monolayer method.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.188-198
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• 1993

We have developed a technique for growing thin oxides (6~10 nm) by the Last step TCA method. N-channel metal-oxide-semiconductor (n-MOS) capacitor and n-channel metal-oxide-semiconductor field-effect transistor's (MOSFET's) having a gate oxide with chlorine incorporated $SiO_2/Si$ interface have been analyzed by electrical measurements and physical methods, such as secondary ion mass spectrometry (SIMS) and electron spectroscopy for chemical analysis (ESCA). The gate oxide grown with the Last strp TCA method has good characteristics as follows: the electron mobility of the MOSFET's with the Last step TCA method was increased by about 7% and the defect density at the $SiO_2/Si$ interface decreases slightly compared with that with No TCA method. In reliability estimation, the breakdown field was 18 MV/cm, 0.6 MV/cm higher than that of the gate oxide with No TCA method, and the lifetime estimated by TDDB measurement was longer than 20 years. The device lifetime estimated from hot-carrier reliability was proven to be enhanced. As the results, the gate oxide having a $SiO_2/Si$ interface incorporated with chlorine has good characteristics. Our new technique of Last step TCA method may be used to improve the endurance and retention of MOSFET's and to alleviate the degradation of thin oxides in short-channel MOS devices.