• Title/Summary/Keyword: fault lines

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Logic Circuit Fault Models Detectable by Neural Network Diagnosis

  • Tatsumi, Hisayuki;Murai, Yasuyuki;Tsuji, Hiroyuki;Tokumasu, Shinji;Miyakawa, Masahiro
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09a
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    • pp.154-157
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    • 2003
  • In order for testing faults of combinatorial logic circuit, the authors have developed a new diagnosis method: "Neural Network (NN) fault diagnosis", based on fm error back propagation functions. This method has proved the capability to test gate faults of wider range including so called SSA (single stuck-at) faults, without assuming neither any set of test data nor diagnosis dictionaries. In this paper, it is further shown that what kind of fault models can be detected in the NN fault diagnosis, and the simply modified one can extend to test delay faults, e.g. logic hazard as long as the delays are confined to those due to gates, not to signal lines.

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The field-test for single line-to-ground fault by an artificial fault generator (인공고장 발생장치(AFG)를 이용한 지락고장 실증시험)

  • Choi, Sun-Kyu;Kim, Dong-Myung;Kang, Moon-Ho
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2004.11a
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    • pp.97-100
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    • 2004
  • This paper introduced an artificial fault generator which was operated in the Go-Chang field-test center and explained the result of single line-to-ground fault by AFG. The AFG can basically experiment line-to-line and line-to-ground faults. This facility directly connected distribution transmission lines, so the test results are very useful for power system analysis and protection. Using the function of the AFG, we briefly said the test methods ud results for the 22.9[kV-v] and $6.6[kV-{\Delta}]$ system.

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Operating Characteristics of Transformer Type SFCL with Resistor in Tertiary Winding (3차 권선에 저항을 사용한 변압기형 전류제한기의 동작 특성)

  • Choi, Byoung-Hwan;Han, Byoung-Sung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.12
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    • pp.1111-1117
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    • 2008
  • A transformer type superconducting fault current limiter (SFCL) is one of the fault current limiters which have been proposed to reduce the fault current in the transmission lines. This paper proposes the new circuit configuration of a transformer type SFCL and also investigates the operating characteristics of the transformer type SFCL containig the resistor in the tertiary winding. The proposed SFCL contains the resistor in the tertiary winding. The newly inserted resistor can divert the power which the High-Tc superconducting has to bear. Because the resistor in the tertiary winding relieves the power of the High-Tc superconducting, it is possible that the proposed transformer type SFCL can decrease the more larger fault current than the conventional SFCL with the same High-Tc superconducting. And the cost of the proposed transformer type SFCL can be reduced.

Load Flow Calculation and Short Circuit Fault Transients in AC Electrified Railways

  • Hosseini, Seyed Hossein;Shahnia, Farhad
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2203-2206
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    • 2005
  • A load flow and short circuit fault simulation of AC electrified railway distribution systems is presented with DIgSILENT PowerFactory software. Load flow of electrified railways distribution system with concerning multi train lines and dynamic characteristics of train load is studied for different time laps. The dynamic characteristics of train load in starting and braking conditions with different starting and stopping times and its moving positions makes the load flow complicated so there is a great need in studying the effects of electrified railways on load flow. Short circuit fault transients is also studied and simulated for both power system or traction distribution system and their effects on the operation of the train sets is investigated.

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Estimation of Fault Location on a Power Line using the Time-Frequency Domain Reflectometry (절연전선 결함 위치 추정에 대한 시간-주파수 영역 반사파 계측법의 적용)

  • Doo, Seung-Ho;Kwak, Ki-Seok;Park, Jin-Bae
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.2
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    • pp.268-275
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    • 2008
  • In this paper, we introduce a new method for detecting and estimating faults on a power line using the time-frequency domain reflectometry system. The system rests upon time-frequency signal analysis and uses a chirp signal which is multiplied by Gaussian envelope. The chirp signal is used as a reference signal, and we can get the reflected signal from a fault on a wire. To detect and estimate faults, we analyze the reflected signal by Wigner time-frequency distribution function and normalized time-frequency cross correlation function. In this paper we design an optimal reference signal for power line and implement a system for estimating fault distance on a power line with the TFDR implemented by PXI equipments. This approach is verified by some experiments with HIV 2.25mm power lines.

A Study on the Fault Location Algorithms on Transmission Line (송전선로의 고장점 검출방법에 관한 연구)

  • Song, Myoung-Gon;Oh, Yong-Taek
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.28 no.4
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    • pp.36-41
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    • 2014
  • Most faults that occur on transmission lines are caused by extreme weather with lightning storms in the distance. These are not only prolongs the time of removing and recovering, but also increases economical damages. If faults can be precisely located, maintenance crews can reach them quickly, and remove the faults in time. So, the precise locating of the faulted point on a transmission line is very important to improve the system reliability, and decreases economic damages as an inherent consequence of long term outages. Also, fault location methods are becoming of much importance for utilities and research. In this paper, two single-terminal impedance-based fault location techniques will be investigated to show the reliability and evaluated the performance of reactance and Takagi method by using MATHCAD program simulations.

On Setting Method of the operating Parameters of SFCL in Transmission Systems Considering Power Protection Relay (계통보호릴레이와의 협조를 고려한 SFCL의 동작파라메타 설정방법에 대한고찰)

  • Hong, Won-Pyo
    • Proceedings of the KIEE Conference
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    • 1998.07c
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    • pp.1231-1234
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    • 1998
  • Design & Operation of power system for meeting increase of electric power demand is becoming more difficult and complex. One of reasons is increase of fault current. As one of the most effective methods for suppressing the fault current, installation of SFCL is expected. This paper describes a method of fault analyses of power system with SFCLs, and also discusses determination of specification of SFCLs, effects of limiting the fault current due to SFCLs by use of the model system of two - bus electric power system with parallel circuit model transmission line. Also, describes the definition of six specific parameters of SFCL for power system application & a proposal of design method of specific parameter of a resistance type SFCL in overhead transmission lines considering operation of protective relays.

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Disribution of quench progress in thin film superconducting fault current limiters (박막형 초전도 한류기에서의 퀜치진행 분포)

  • 김혜림;현옥배;최효상;황시돌;김상준
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.226-229
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    • 2000
  • We fabricated thin film superconducting fault current limiters based on YBa$_2$Cu$_3$O$_{7}$ thin films and investigated the distribution of quench progress in the limiters. The limiters were tested with simulated fault currents. Quench progress depended significantly on the position in the limiter with respect to electrodes as well as the fault current magnitude. The heat transfer from limiter meander lines to electrodes explains these results.s.

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Circuit partitioning to enhance the fault coverage for combinational logic (조합논리회로의 고장 검출율 개선을 위한 회로분할기법)

  • 노정호;김상진;이창희;윤태진;안광선
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.4
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    • pp.1-10
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    • 1998
  • Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

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Fault Location Algorithm for Parallel Transmission Line with a Teed Circuit (1회선 분기점을 갖는 병행 2회선 송전선로의 고장점 표정 알고리즘)

  • Kwon, Tae-Won;Kang, Sang-Hee;Choi, Myeon-Song;Lee, Seung-Jae
    • Proceedings of the KIEE Conference
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    • 1999.11b
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    • pp.116-118
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    • 1999
  • A fault location algorithm that is suitable for parallel transmission line which contains a teed circuit is presented. The method uses only the local end voltage and current signals. Zero sequence currents of other lines are calculated by distribution factors, and distance equations are solved by recursive calculation.

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