• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권1호
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• Proceedings of the Korea Society for Industrial Systems Conference
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• 한국산업정보학회 1997년도 추계학술대회 발표논문집:21세기를 향한 정보통신 기술의 전망
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• pp.417-433
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• 1997

A real-time operating system has focused primary on techniques to minimize processing time, with a secondary emphasis on system reliability issues. Conversely, fault-tolerant system has concentrated on using recourse and information redundancy to maximize the availability and reliability of the system, with a lesser emphasis on performance. We have developed a fault-tolerant and real-time operations system which support a powerful concurrent runtime environment under the above requirements. In this paper, we present an overview of real-time systems, design and implementation of a duplex architecture using advanced concepts and technologies such as fast " fault detection", "fault isolation" and "fault recovery" Because the duplex architecture has two dentical hardware elements and has several recovery steps and hierarchy to facilitate a fast recovery which must be proceeded by a prompt fault detection and isolation. Thus it makes possible to minimize the overhead of the systems including hardware and software and guarantee the service continuity of he systems.

• Journal of Ubiquitous Convergence Technology
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• 제2권1호
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• pp.12-17
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• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.

• Journal of the Semiconductor & Display Technology
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• 제18권3호
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• pp.140-143
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• 2019

The Internet has been expanded constantly and greatly such that we are having vast number of web pages with dynamic changes. Especially, the fast development of wireless communication technology and the wide spread of various smart devices enable information being created at speed and changed anywhere, anytime. In this situation, web crawling, also known as web scraping, which is an organized, automated computer system for systematically navigating web pages residing on the web and for automatically searching and indexing information, has been inevitably used broadly in many fields today. This paper aims to implement a prototype web crawler with Python and to improve the execution speed using threads on multicore CPU. The results of the implementation confirmed the operation with crawling reference web sites and the performance improvement by evaluating the execution speed on the different thread configurations on multicore CPU.

• The Journal of Information Systems
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• 제14권3호
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• pp.97-104
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• 2005

The paper proposes an implementation architecture of DiffServ-over-MPLS traffic engineering (TE) on Intel IXP2400 network processor using Intel IXA SDK 4.0 Framework. Program architecture and functions are described. Also fast and scalable range-match classification scheme is proposed for DiffServ-over-MPLS TE that has been integrated with functional blocks from Intel Microblocks library. Performance test shows that application can process packets at approximate data rate of 3.5 Gbps. The proposed implementation architecture of DiffServ-over-MPLS TE on Network processor can provide guaranteed QoS on high-speed next generation Internet, while being flexible and easily modifiable.

• The Transactions of the Korean Institute of Electrical Engineers
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• 제40권4호
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• pp.331-341
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• 1991

The discrete cosine transform (DCT) is widely used in many signal processing areas, including image and speech data compression. In this paper, we investigate a fixed-point error analysis for fast DCT algorithms, namely, Lee [6], Hou [7] and Vetterli [8]. A statistical model for fixed-point error is analyzed to predict the output noise due to the fixed-point implementation. This paper deals with two's complement fixed-point data representation with truncation and rounding. For a comparison purpose, we also investigate the direct form DCT algorithm. We also propose a suitable scaling model for the fixed-point implementation to avoid an overflow occurring in the addition operation. Computer simulation results reveal that there is a close agreement between the theoretical and the experimental results. The result shows that Vetterli's algorithm is better than the other algorithms in terms of SNR.

• Journal of the Korean Institute of Telematics and Electronics S
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• 제34S권1호
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• pp.124-131
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• 1997

There have been many demands for th ereal-time image compression. The image compression systems have a wide range of applications. However, real-time encoding is hard to implement because it needs a large amount of computations. In particular, the discrete cosine transform (DCT) and motion estimatio require a large number of arithmetic oeprations compared to other algorithms in MPEG-2. The conventional fasdt DCT algorithms have focused on the reduction of the number of additions more cycles and more expense in realization. Because TMS320C80 has special structure, new approach for implementation of DCT is suggested. The selection of adaptive algorithm and optimization is requried TMS320C80 are analyzed an dsome adaptive DCT algorithms are selected. The DCT algorithms are optimized and implemented. Chens and lees DCT algorithms among various fast algorithms are selected because 1-D approach is effective in the view of th einternal structure of TMS320C80. According to the simulation result, Lees algorithm is more effective in speed and has little difference in precision. On the basis of the result, the possibility of DCT implementation for real-time MPEG-2 system is verified and the required number of the processor, called advanced DSP, is decided for real-time MPEG-2 encoding and decoding.

• Transactions of the Korean Society of Machine Tool Engineers
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• 제10권2호
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• pp.38-47
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• 2001

In this paper, a new scheme of adaptive-neuro control system is presented to implement real-time control of robot manipulator using Digital Signal Processors. Digital signal processors, DSPs, are micro-processors that are particularly developed for fast numerical computations involving sums and products of measured variables, thus it can be programmed and executed through DSPs. In addition, DSPs are as fast in computation as most 32-bit micro-processors and yet at a fraction of therir prices. These features make DSPs a viable computational tool in digital implementation of sophisticated controllers. Unlike the well-established theory for the adaptive control of linear systems, there exists relatively little general theory for the adaptive control of nonlinear systems. Adaptive control technique is essential for providing a stable and robust perfor-mance for application of robot control. The proposed neuro control algorithm is one of learning a model based error back-propagation scheme using Lyapunov stability analysis method.The proposed adaptive-neuro control scheme is illustrated to be a efficient control scheme for the implementation of real-time control of robot system by the simulation and experi-ment.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제5권12호
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• pp.2326-2339
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• 2011

To reduce the implementation complexity of the Vertical Bell Labs layered space-time (V-BLAST) systems with respect to the zero-forcing (ZF) criterion, a computationally efficient recursive algorithm is proposed. A fast implementation of the proposed algorithm is developed and its complexity is analyzed in detail. The proposed algorithm matches the ZF-OSIC detection well, and its three significant advantages can be demonstrated by analyses and simulations. Firstly, its speedups over the conventional ZF-OSIC with norm-based ordering, the original fast recursive algorithm (FRA) and the fastest known algorithm (FKA) in the number of flops are 1.58, 2.33 and 1.22, respectively. Secondly, a much simpler implementation than FRA and FKA can be expected. Finally, the storage requirements are lower than those of FRA and FKA. These advantages make the proposed algorithm more efficient and practical.