• 한국통신학회:학술대회논문집
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• 한국통신학회 1986년도 추계학술발표회 논문집
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• pp.28-34
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• 1986

The frequency synthesizer for Fast Frequency Hopping System musy be capable of a fast tuning with a small step frequency over wide band. The most conventional frequency synthesizer that uses the phase locked loop (PLL) enables the wide band problem but have a poor side of the low resolution and the transient response. In this paper, we have discussed the experimental results of a direct digital frequency synthesizer which can be applicable to the Fast Frequency Hopping System, using digital-to-analoq (D/A)conversion techniques. With this system we can find the merits of a fine resolution and the possibility of a fast tuning leaving the problems of transent frequency.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권2호
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• pp.601-617
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• 2014

In digital radio broadcasting systems, long delays are incurred in service start time when tuning to a particular frequency because several synchronization steps, such as symbol timing synchronization, frame synchronization, and carrier frequency offset and sampling frequency offset compensation are necessary. Therefore, the operation of the synchronization blocks causes delays ranging from several hundred milliseconds to a few seconds until the start of the radio service after frequency tuning. Furthermore, if spectrum inversed signals are transmitted in digital radio broadcasting systems, the receivers are unable to decode them, even though most receivers can demodulate the spectral inversed signals in analog radio broadcasting systems. Accordingly, fast synchronization techniques and a method for spectral inversion detection are required in digital radio broadcasting systems that are to replace the analog radio systems. This paper presents a joint detection method of frame, integer carrier frequency offset, and spectrum inversion for DRM Plus digital broadcasting systems. The proposed scheme can detect the frame and determine whether the signal is normal or spectral inversed without any carrier frequency offset and sampling frequency offset compensation, enabling fast frame synchronization. The proposed method shows outstanding performance in environments where symbol timing offsets and sampling frequency offsets exist.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• 대한전자공학회논문지SD
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• 제43권9호
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• pp.10-16
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• 2006

본 논문에서는 PHS 어플리케이션에서 새로운 Coarse Toning 기법을 사용한 빠른 스위칭의 CMOS 주파수 합성기를 기술하였다. 제안한 Coarse Tuning 방법은 Phase Noise와 Lock-Time을 최적화하기 위해 LC-VCO의 적절한 Tuning Capacitances를 선택하는 것이다. 이를 바탕으로 측정된 Lock-Time은 약 $20{\mu}s$ 이고, Phase Noise는 600kHz의 offset에서 -121dBc/Hz이다. 칩은 $0.25{\mu}m$ CMOS 공정으로 제작하였고, 면적은 $0.7mm{\times}2.1mm$ 이다. 소비전력은 2.7V 공급 전압 하에서 54mW 이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• 한국소음진동공학회논문집
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• 제15권8호
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• pp.954-961
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• 2005

This paper is concerned with the implementation of auto-tuning positive position feedback controller using a digital signal processor and microcontroller. The main advantage of the positive position feedback controller is that it can control a natural mode of interest by tuning the filter frequency of the positive position feedback controller to the natural frequency of the target mode. However, the positive position feedback controller loses its advantage when mistuned. In this paper, the fast fourier transform algorithm is implemented on the microcontroller whereas the positive position feedback controller is implemented on the digital signal processor. After calculating the frequency which affects the vibrations of structure most, the result is transferred to the digital signal processor. The digital signal processor updates the information on the frequency to be controlled so that it can cope with both internal and external changes. The proposed scheme was installed and tested using a beam equipped with piezoceramic sensor and actuator. The experimental results show that the auto-tuning positive position feedback controller proposed in this paper can suppress vibrations even when the target structure undergoes structural change thus validating the approach.

• Journal of Power Electronics
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• 제12권6호
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• pp.851-858
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• 2012

This paper presents resonant inverter tuning for current source parallel resonant induction heating systems based on a new self oscillating switching technique. The phase error is suppressed in a wide range of operating frequencies in comparison with Phase Locked Loop (PLL) techniques. The proposed switching method has the capability of tuning under fast changes in the resonant frequency. According to this switching method, a multi-frequency induction heating (IH) system is proposed by using a single inverter. In comparison with multi-level inverter based IH systems, the advantages of this technique are its simple structure, better transients and wide range of operating frequencies. A laboratory prototype was built with an operating frequency of 35 kHz to 55 kHz and 300 W of output power. The performance of the IH system shows the validity of the new switching technique.

• Journal of Power Electronics
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• 제16권4호
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• pp.1513-1525
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• 2016

Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.409-411
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• 2007

This paper deals with an automatic tuning method of the notch filter to suppress oscillations in a permanent magnet linear synchronous motor(PMLSM) drive. First, it saves automatically the reference torque-component current when oscillations are detected. Then the oscillation frequency of the saved data is calculated by using the fast Fourier transform(FFT) algorithm. And also the Hanning function is used to reduce the leakage components due to the aperiodic measurement data. Finally, the proposed method tunes the notch filter to suppress oscillations. Experimental results on the test rig show the validity of the proposed method.

• 한국산학기술학회논문지
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• 제14권7호
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• pp.3425-3430
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• 2013

최근 이동통신 시장의 급속한 증가에 따라 단말기 설계는 다표준 방식으로 발전하고 있다. 본 논문에서는 다표준 이동통신 시스템에 적용할 수 있는 주파수 가변형 능동 RC 대역통과 필터를 능동 인덕터를 사용하여 설계하였다. 기존의 대역통과 필터 설계법에서는 저지대역의 감쇠 특성과 통과대역의 주파수 선택도를 향상시키기 위하여 필터의 차수를 높게 하거나 극점 Q를 증가시키는 설계법을 사용한다. 본 논문에서는 극점 Q가 높은 능동 인덕터로 대역통과 필터를 설계하여 주파수 특성이 향상되었다. 또한 설계된 대역통과 필터는 튜닝 회로를 이용하여 필터의 중심주파수와 이득을 간단히 조절할 수 있도록 제안하였다. 설계된 능동 RC 대역통과 필터 특성은 TSMC $0.18{\mu}m$ 공정 파라미터를 이용하여 해석하였다. 시뮬레이션 결과, Q=20.5를 갖는 능동 인덕터를 이용한 필터는 1.86GHz 중심주파수에서 90MHz의 대역폭을 갖고, 튜닝 회로의 커패시터 값으로 중심주파수를 1.86~2.38GHz 범위까지 튜닝이 가능하여 다표준 무선통신 시스템에 적용할 수 있다.