• Journal of Powder Materials
• /
• v.8 no.2
• /
• pp.110-116
• /
• 2001

Abstract To investigate the effect of mechanical alloying process to thermoelectric properties of PbTe sintered body, Pb-Te mixed powder with Pb : Te : 1 : 1 composition was mechanically alloyed using tumbler-ball mill. Thermoelectric properties of the sintered body were evaluated by measuring of the Seebeck coefficient and specific electric resistivity from the room temperature to 50$0^{\circ}C$. Sintered body of only mechanically alloyed PbTe powder showed p-type behavior at the room temperature, and occurred type transition from p-type to n-type at about 30$0^{\circ}C$. PbTe sintered body which was fabricated using heat treated powder in $H_2$ atmosphere after mechanical alloying showed stable n-type behavior under 50$0^{\circ}C$. N-type PbTe sintered body fabricated by mechanical alloying process had 4 times higher power factor than that fabricated by the melt-crushing process. Application of a mechanical alloying process to fabricate of n-type PbTe thermoelectric material seemed to be useful to increase the power factor of PbTe sintered body.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.741-744
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.101-104
• /
• 1998

A new planar-type micro gas sensor was designed and fabricated on silicon substrate and the operating characteristics of the sensor were investigated. The thin sensitive film of the sensor was fabricated by spin-coating of the SnO$_2$ sol solution which was synthesized by hydrothermal method. The spin-coating method for preparation of sensing layer was adopted to improve the long-term stability of the fabricated sensing film instead of physical methods such as rf sputtering and thermal evaporation. The fabricated microsensor showed a fairly good sensing performance for CO gas in air at 250$^{\circ}C$ The sensitivity(S=Ra/Rg) was shown to be about 5 to 2000ppm CO with heating power of 50mW.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.739-742
• /
• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• Journal of the Optical Society of Korea
• /
• v.18 no.6
• /
• pp.762-765
• /
• 2014

We fabricated a periodically poled lithium niobate (PPLN) by direct laser-writing of a quasi-phase-matching (QPM) structure in photolithographic process. Because we do not need to prepare a photomask by electron-beam writing, the "maskless" process shortens the fabrication time and significantly reduces the cost. We evaluated the poling quality of the direct laser-written PPLN by measuring the diffraction noise from the surface relief pattern of the fabricated QPM grating and comparing the results to those from a conventional PPLN made with a photomask. The quality of the PPLN fabricated by direct laser-writing was shown to be equivalent to that fabricated by the conventional method.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1440-1442
• /
• 2005

We have fabricated vertical type organic thin film transistors (OTFTs) using organic semiconductor materials such as F16CuPc, NTCDA, PTCDI C-8 and C60. The layers of OTFT were fabricated by vacuum evaporation technique and spin casting method onto the Indium Tin Oxide (ITO) coated glass. I-V characteristics and on-off ratios of the fabricated OTFTs were investigated. In addition, we have fabricated light emitting transistor using MEH-PPV and then investigated EL electroluminescent properties.

• Electrical & Electronic Materials
• /
• v.9 no.6
• /
• pp.600-604
• /
• 1996

High-T$_{c}$, superconducting wire is very important element for the application of electrical power systems. But it is very difficult to develope the long high T, wire with excellent properties. BiSrCaCuO multi-layer tapes are fabricated by a rolling method and pressing method sintered for several step at 840.deg. C. The critical current densities of 637 filament multi-layer tapes sintering 100 hours fabricated by the rolling method and pressing method are 1.3*10$^{4}$ A/cm$^{2}$ and 5.5*10$^{3}$ A/cm$^{2}$. The critical cur-rent densites of multi-layer tapes made by rolling method are found to be better than those fabricated by the powder-in-tube method and pressing process. As result, the rolling method is the best way to fabricated the multi-layer filament.t.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1890-1892
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.4
• /
• pp.338-342
• /
• 2010

Carbon nanotubes (CNTs) have excellent electrical, chemical stability, mechanical and thermal properties. The MWCNT films were investigated as a transparent electrode for the solar cell, OLED, and field-emission display. MWCNT films were fabricated by air spray method, whose process is quite low-costed, using the multi-walled CNTs solution on glass substrates. Moreover, the most stable film was fabricated when the spraying time was 60 sec. The film that was sprayed with the MWCNT dispersion for 60 sec, has 300nm thick. And its electric resistivity, transmittance rate, mobility and carrier concentration are $6{\times}10^{-2}{\Omega}{\cdot}cm$, 50% at ${\lambda}=550mm$, $4.3{\times}10^{-2}cm^2/V{\cdot}s$ and $2.1{\times}10^{21}cm^{-3}$, respectively. Also, absorption energy of MWCNT films show from 3.9 eV to 4.6 eV. Furthermore, we can use MWCNT films fabricated by the spray method for the transparent electrode.

• Proceedings of the KIEE Conference
• /
• 1993.11a
• /
• pp.192-194
• /
• 1993

In this paper, a silicon piezoresistive accelerometer of which the cantilevers have uniform thickness is designed and fabricated with SOI wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW etchant. The fabrication processes are that of the frontside processes including the etching of the cantilevers and the doubleside alignment holes, the diffusion of the piezoresisters and patterning of the contact windows, and the metal connection process, and that of the backside processes including the etching of the shallow cavity and the seismic mass. Because of the uniformity of thickness, the performance of the accelerometer fabricated with SOI wafer is expected to be better than that of accelerometer fabricated by the time-controlled etching method.