• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.5
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• pp.1316-1332
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• 2012

Formation flying is an important technology that enables high cost-effective organization of outer space aircrafts. The ad-hoc wireless network based on direct-sequence ultra-wideband (DS-UWB) techniques is seen as an effective means of establishing wireless communication links between aircrafts. In this paper, based on the theory of matched filter and error bits correction, a hybrid detection algorithm is proposed for realizing multiuser detection (MUD) when the DS-UWB technique is used in the ad-hoc wireless network. The matched filter is used to generate a candidate code set which may contain several error bits. The error bits are then recognized and corrected by an novel error-bit corrector, which consists of two steps: code mapping and clustering. In the former step, based on the modified optimum MUD decision function, a novel mapping function is presented that maps the output candidate codes into a feature space for differentiating the right and wrong codes. In the latter step, the codes are clustered into the right and wrong sets by using the K-means clustering approach. Additionally, in order to prevent some right codes being wrongly classified, a sign judgment method is proposed that reduces the bit error rate (BER) of the system. Compared with the traditional detection approaches, e.g., matched filter, minimum mean square error (MMSE) and decorrelation receiver (DEC), the proposed algorithm can considerably improve the BER performance of the system because of its high probability of recognizing wrong codes. Simulation results show that the proposed algorithm can almost achieve the BER performance of the optimum MUD (OMD). Furthermore, compared with OMD, the proposed algorithm has lower computational complexity, and its BER performance is less sensitive to the number of users.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.44-46
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. We proposal Algorithm use The Extended Kalman filter. The Kalman filter reduce measurement noise. Therefore, By using this error reduction method following results are obtained; the effect of measurement nois of Pixel is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.129-133
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers and fuzzy rules. Therefore, By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.794-806
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• 2004

This paper deals with correction of frequency offset and analysis of quantization angle noise in the IEEE 802.1la OFDM system. The rotation phase per symbol due to the carrier frequency offset is estimated from auto-correlation of the short Preambles, which are over-sampled for the reduction of noise in OFDM signals. The pilot signals are introduced to estimate the rotation phase per OFDM symbol due to estimation error of the carrier frequency offset and the sampling frequency onset. During the estimation and correction of the frequency onsets, a CORDIC processor and a look-up table are used for the conversion between a rotation phase and its complex number. Being calculated by a limited number of bits in the CORDIC processor and the look-up table, the rotation phase and its complex number have quantization angle errors. The quantization errors are analyzed as SNR (signal to noise ratio) due to the quantization bit numbers. The minimum bit number is suggested to meet the specification of IEEE 802.1la properly. Finally, the quantization errors are evaluated through simulations on number of quantization bits and SNR of received signals.