• 한국통신학회논문지
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• 제33권12C호
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• pp.1014-1020
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• 2008

메모리 등의 저장 장치는 다양한 전자제품에 널리 이용되면서 높은 메모리 집적도가 요구되고 있으며 멀티 레벨로 데이터를 저장하는 단계에 이르렀다. 그 결과 데이터의 오류율은 더 높아지게 되었다. 본 논문에서 우리는 저장장치의 낮은 오류율을 만족시키기 위하여 통신시스템에서 널리 사용되고 있는 오류정정부호 기법을 적용하였다. 평균 오류율 (BER)이 $10^{-5}$ 또는 $5{\times}10^{-6}$인 AWGN 채널에서 4-level cell을 이용한 저장장치에 대하여 목표 부호율 0.99과 목표 오류율 (BER) $10^{-11}$과 $10^{-13}$를 만족시킬 수 있는 방법을 알아본다. 높은 부호율에서는 연접부호의 성능이 블록 부호만 사용한 경우보다 좋지 않은 경우도 많으며, 이때 천공을 많이 한 경우에도 성능 열화가 덜한 안쪽 부호를 선정하는 것이 중요함을 확인하였다. 일반적인 feedfoward systematic 길쌈 부호를 이용한 연접부호는 복잡도를 고려하지 않더라도 블록 부호를 단독으로 사용한 경우보다 성능이 좋지 않음을 확인하였고, 높은부호율 에서도 성능이 우수한 천공 길쌈 부호를 만들기 위해서는 RSC 부호를 사용해야 한다는 것을 모의실험 결과를 통해 보여준다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권4호
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• 대한수학회보
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• 제57권2호
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• pp.295-309
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• 2020

Loop transversal codes take an alternative approach to the theory of error-correcting codes, placing emphasis on the set of errors that are to be corrected. Hitherto, the loop transversal code method has been restricted to linear codes. The goal of the current paper is to extend the conceptual framework of loop transversal codes to admit nonlinear codes. We present a natural example of this nonlinearity among perfect single-error correcting codes that exhibit efficient domination in a circulant graph, and contrast it with linear codes in a similar context.

• 한국통신학회논문지
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• 제31권4C호
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• pp.426-433
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• 2006

본 논문에서는 이중이진 터보부호를 오류정정부호로 사용하는 이중이진 터보 incremental redundancy(IR)-hybrid ARQ(HARQ)기법을 제안한다. 또한 HARQ의 성능파라미터인 처리율의 기본적 해석 방법을 제시한다. 제안된 이중이진 터보 IR-HARQ는 이진 터보부호를 사용하는 IR-HARQ에 비해 모든 $E_s/N_0$ 영역에서 향상된 처리율을 보이며 오류정정부호만을 사용하는 경우에 비해 부호화 이득을 향상시킨다.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송∙미디어공학회 2020년도 추계학술대회
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• pp.241-243
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• 2020

The high computational complexity of deep learning algorithms has led to the development of specialized hardware architectures. However, soft errors (bit flip) may occur in these hardware systems due to voltage variation and high energy particles. Many error correction methods have been proposed to counter this problem. In this work, we analyze an error correction mechanism based on repetition codes and an activation function. We test this method by injecting errors into weight filters and define an ideal error rate range in which the proposed method complements the accuracy of the model in the presence of error.

• ETRI Journal
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• 제45권3호
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• pp.404-417
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• 2023

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10^-10 at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10^-7 at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10^-6 at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

• 호남수학학술지
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• 제30권1호
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• pp.33-45
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• 2008

Lee weight is more appropriate for some practical situations than Hamming weight as it takes into account magnitude of each digit of the word. In this paper, we obtain a sufficient condition over the number of parity check digits for codes correcting random errors and simultaneously detecting burst errors with Lee weight consideration.

• 대한전자공학회논문지
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• 제23권3호
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• pp.309-316
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• 1986

A concatenated coding system using a binary code as the inner code and a nonbinary code as the outer code has been constructed for the purpose of error correction. The complexity of a conventional coding system grows exponentially as the code length of a block code becomes longer. To reduce the complexity for ling code, an effective communication system has been proposed by cascading two codes-binary and norbinary codes. Using a parallel-to-serial circuit and a serial-to-parallel circuit, the concatenated coding system has been designed and constructed by empolying a (7,3) burst error correcting code as the inner code and a (7,3) Reed-Solomon code as the outer code. This system has been simulated and tested using a micro-computer. For the (49,9) concatenated coding system, the error probability of the channel has been evaluated and compared to different coding systems.