• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.6
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• pp.313-316
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• 2006

A method for evaluation of the linearity of both the ratio error and phase angle error in the current transformer(CT) comparison measurement equipment has been developed by employing the standard resistors with negligible AC-DC resistance difference less than $10^{-5}$. The non-reactive standard resistors for the linearity check of the system are used as the external burden connected with the secondary of CT under test. These burdens consist of nine standard resistors, with the nominal resistance of $0.01{\Omega},\;0.1{\Omega},\;0.2{\Omega},\;0.4{\Omega},\;0.6{\Omega},\;1{\Omega},\;2{\Omega},\;4{\Omega}$, and $10{\Omega}$. For linearity check, the developed method has been applied in the CT comparison measurement equipment belonging to the industry.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.2
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• pp.180-184
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• 2009

The memory is very sensitive to the soft error because the integration of the memory increases under low power environment. Error correcting codes (ECCs) are commonly used to protect against the soft errors. This paper proposes a new genetic ECC design method which reduces power consumption. Power is minimized using the degrees of freedom in selecting the parity check matrix of the ECCs. Therefore, the genetic algorithm which has the novel genetic operators tailored for this formulation is employed to solve the non-linear power optimization problem. Experiments are performed with Hamming code and Hsiao code to illustrate the performance of the proposed method.

• Journal of IKEEE
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• v.26 no.3
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• pp.437-444
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• 2022

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. In automotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatal results may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C, there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in this paper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and the verification is presented by designing it in hardware.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.681-684
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• 2008

Bluetooth baseband performs FEC (forward error check) at the interface of transmitter and receiver modem. Well-designed FEC means directly the efficiency of retransmission of the data payload therefore design optimization is very important. In this paper, we designed a optimal 1/3, 2/3 type of FEC. 1/3 FEC. which performs 3 times customary repetition was designed for packet header, and 2/3 FEC was designed for data packets with (15, 10) reduced hamming code. The proposed hardware FEC block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized FEC block operated at 40Mhz normal clock speed of the target baseband microcontroller.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.215-218
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• 1998

In this paper, we design the $H_{\infty}$ controllers satisfying robust stability and performance for underwater vehicle. The underwater vehicle has computations delay time and input delay. In addition, there exist parameter uncertainties by the roll motion coefficient error, buoyance error, and gravity error. We design the $H_{\infty}$ controllers using model-matching method and check the performance of the proposed controller by nonlinear simulation which includes time delay model, sensor error model, and actuator model.