• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1681-1684
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• 2004

90 년대 후반부터 웹 기반 수업(Web-based instruction)이라 하여 인터넷을 이용한 새로운 교육방법이 시도되었다. WBI에 필요한 각종 프로그래밍을 수작업으로 진행하여야 한다는 문제점을 극복하기 위해 개발된 학습운영체제(Learning Management System)가 개발되면서 인터넷을 통한 교육은 급속히 확산되고 있다. 무선 인터넷 기술까지 수용하는 개념인 소위 e-Learning 체제로 발전되면서 e-Learning의 수요는 급속히 증가하게 되었다. e-Learning 기술 표준 개발을 실질적으로 주도하는 기관들인 IEEE, AICC, IMS가 제안하는 개별 표준안들을 ADL에서 SCORM(Sharable Content Object Reference Model)이라는 종합적인 표준안으로 수렴하게 되면서 SCORM을 기준으로 만든 다양한 컨텐츠가 개발되고있다.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• Journal of Engineering Education Research
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• v.24 no.5
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• pp.38-45
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• 2021

The CanSat was designed as an educational satellite simulation program that implements the overall system of the satellite such as the command processing unit, the communication unit, and the power unit in a structure of the size of a can. In particular, the training effect is very excellent because the trainee can learn a process similar to the actual satellite development process by designing, manufacturing, testing, and launching. Republic of Korea Air Force Academy has been using the CanSat production kit used by the domestic can satellite contest experience department for education, but since it was produced based on PCB, it was impossible to show creativity and operation was restricted even with small mistakes. In this paper, we analyze the existing CanSat kit and propose a new educational CanSat kit that can be used in creative engineering design and practice subjects that will be reorganized into a regular course from 2021, and a lesson plan. In conclusion, by using the proposed CanSat kit for lectures, it is possible to achieve educational purposes and effects, improve lecture satisfaction, and provide stable instruction.

• Proceedings of the KOSOMBE Conference
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• v.1994 no.12
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• pp.92-95
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• 1994

As computer systems to make medical practice easy are widely used, a special hardware system processing medical data fast becomes more important. To meet the urgent demand for high speed image processing, especially image compression and decompression, we designed and implemented the medical image CODEC (COder/BECoder) based on MISD(Multiple Instruction Single Data stream) architecture to adopt parallelism in it. Considering not being a standart scheme of medical mage compression/decompress ion, the CODEC is designed programable and general. In this paper, we use JPEG (Joint Photographic Experts Group) algorithm to process images fast and evalutate it.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1408-1409
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• 2007

인터넷 기반 분야가 다양화 되고 있는 가운데 교육 분야 또한 웹 활용 교육(WBI, Web Based Instruction)이 시대 흐름을 타고 그 활용도가 높아지고 있다. 인터넷을 통한 교실 중심의 획일적인 교육 분위기에서 벗어나 교육 컨텐츠 수요자 개개인의 자율성을 반영하는 것이 가능한 매체는 드물다. 교육 분야 가운데 특히 공학 교육은 해당 분야에 관한 특수성과 전문성이 요구되어 수요자 중심의 효과적인 교육 컨텐츠 개발에 어려운 요소로 작동한다. 이렇듯 유연한 매체를 이용함에 있어서 게슈탈트 시지각 이론을 적용함으로써 좀더 효과적인 WBI 활용을 유도하는 것은 자원 이용율 측면 및 학업성취도를 높이는데 기여할 수 있겠다. 이에 본 논문에서는 공학 교육을 위한 게슈탈트 시지각 이론 기반 WBI 시스템을 설계하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Journal of Korea Game Society
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• v.10 no.6
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• pp.25-35
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• 2010

The generation who have had experienced computer games while growing up, are called game generation. The game generation has quite different styles of thinking and behavior from other generations. But present education methods for the game generation are not basically different from the education methods for other generations. Prensky argued that digital game-based learning is one of the few ways to meet the needs of the information age for the game generation. In this paper, we analyze the suitability of 4 design methods for educational games in comparison which were selected by the literatures survey. The suitability analysis was performed on the overall design method, the game design method, the education design method, the explicit of the design method, and the pros and cons. We suggest research topics on design methods for educational games which are needed to research in the future, based on the analyzed results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.51-59
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• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

• ETRI Journal
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• v.25 no.5
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.