• The Journal of the Acoustical Society of Korea
• /
• v.19 no.4
• /
• pp.45-51
• /
• 2000

This paper describes real-time implementation of a multi-channel G.729A speech coder using a 16 bit fixed-point Digital Signal Processor (DSP) and its application to a Voice Mailing Service (VMS) system. TMS320C549 by Texas Instruments was used as a fixed point DSP chip and a 4 channel G.729A coder was implemented on the chip. The implemented coder required 14.5 MIPS for the encoder and 3.6 MIPS for the decoder at each channel. In addition, memories required by the coder were 9.88K words and 1.69K words for code and data sections, respectively. As a result, the developed VMS system that accommodates two DSP chips was able to support totally 8 channels. Experimental results showed that the our multi-channel coder passes all of test vectors provided by ITU-T.

• Journal of Navigation and Port Research
• /
• v.28 no.1
• /
• pp.23-29
• /
• 2004

This paper deals with Reed-Solomon Coding for EUROFIX system EUROFIX is an integrated navigation and communication system, which combines Differential GNSS and Loran-C EUROFIX transmits DGNSS(Differential Global Navigation Satellite Systems) (data by pulse position modulation of Loran-C pulses. Loran-C system is regarded as a satellite backup system in recent. And now, it is important to detect and correct much errors in communication systems. Error corrections or correction algorithm is actively studied nowadays because of this. In this paper, we study and design encoder and decoder of Reed Solomon Code using Finite Galois Field Fourier Transformation for error corrections in EUROFIX data transmission. Through extensive simulation, the designed Reed Solomon code is shown to be effective for error correction in EUROFIX data transmission.

• Journal of Broadcast Engineering
• /
• v.15 no.5
• /
• pp.642-652
• /
• 2010

Recently, DVC (Distributed Video Coding) techniques are drawing a lot of interests as one of the future research works to achieve low complexity encoding in various applications. But, due to the limited computational complexity, the performances of DVC algorithms are inferior to those of conventional international standard video coders, which use zig-zag scan, run length code, entropy code and skipped macroblock. In this paper, in order to overcome the performance limit of the DVC system, the distortion for every block is estimated when side information is found at the decoder and then we propose a new selective block encoding scheme which provides the encoder side with the motion information for the highly distorted blocks and then allows the sender to encode the motion compensated frame difference signal. Through computer simulations, it is shown that the coding efficiency of the proposed scheme reaches almost that of the conventional inter-frame coding scheme.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.41 no.12
• /
• pp.1834-1843
• /
• 2016

DVRs are the most common recording and displaying devices used for surveillance. Video compression plays a key role in DVRs for saving storage; the video compression standard, H.264/AVC, has recently become the dominant choice for DVRs. DVRs require various display modes, such as fast-forward, backward play, and pause; these are called trick modes. The implementation of precise trick mode play requires a very high decoding capability or a very intelligent scheme in order to handle the high computation complexity. The complexity is increased in many surveillance applications where more than one camera is used to monitor multiple spots or to monitor the same area using various angles. An implementation of a trick mode play and a frame buffer management scheme for the hardware-based H.264/AVC codec for multi-channel is presented in this paper. The experimental results show that exact trick mode play is possible using a standard H.264/AVC video codec with keyframe encoding feature at the expense of bitstream size increase.

• Journal of KIISE
• /
• v.45 no.1
• /
• pp.94-98
• /
• 2018

We propose Wide Inception ResNet (WIR Net) an optimized neural network architecture as a real-time semantic segmentation method for autonomous driving. The neural network architecture consists of an encoder that extracts features by applying a residual connection and inception module, and a decoder that increases the resolution by using transposed convolution and a low layer feature map. We also improved the performance by applying an ELU activation function and optimized the neural network by reducing the number of layers and increasing the number of filters. The performance evaluations used an NVIDIA Geforce GTX 1080 and TX1 boards to assess the class and category IoU for cityscapes data in the driving environment. The experimental results show that the accuracy of class IoU 53.4, category IoU 81.8 and the execution speed of $640{\times}360$, $720{\times}480$ resolution image processing 17.8fps and 13.0fps on TX1 board.

• Journal of Broadcast Engineering
• /
• v.7 no.4
• /
• pp.327-334
• /
• 2002

This paper addresses an efficient loop filter algorithm to improve visual quality by simultaneously reducing blocking and ringing artifacts in H.26L video coder. H.26L video coding standard using the different coding mechanism to existing video coding standards has different distribution of blocking and ringing artifacts that is dependent on coding type, quantization step size, and motion vector. Therefore, the information is used to define the filter type and the filter coefficients. and a projection operator is defined to avoid the over-smoothness. In addition, in order to avoid over-smoothing coming from filtering processing, a constraint projection operator is defined. Since the above information is available both in encoder and in the decoder, a loop filter is used, and the algorithm is simplified to reduce the computational cost. Experimental results show the capability of the proposed algorithm.

• Journal of Broadcast Engineering
• /
• v.15 no.4
• /
• pp.540-546
• /
• 2010

Since the stereoscopic 3-dimensional (3D) video that provides users with a realistic multimedia service requires twice as much data as 2-dimensional (2D) video, it is difficult to construct the fast system. In this paper, we propose a fast stereoscopic 3D broadcasting system based on the depth information. Before the transmission, we encode the input 2D+depth video using x264, an open source H.264/AVC fast encoder to reduce the size of the data. At the receiver, we decode the transmitted bitstream in real time using a compute unified device architecture (CUDA) video decoder API on NVIDIA graphics processing unit (GPU). Then, we apply a fast view synthesis method that generates the virtual view using GPU. The proposed system can display the output video in both 2DTV and 3DTV. From the experiment, we verified that the proposed system can service the stereoscopic 3D contents in 24 frames per second at most.

• Journal of Digital Contents Society
• /
• v.5 no.3
• /
• pp.199-204
• /
• 2004

A problem of many fractal image compression algorithms providing good quality at low bit rate is that the decoding time rests on an iterative procedure whose complexity is imag-dependent. This paper proposes an iterative-free fractal image decoding algorithm to reduce the decoding time. In the proposed method, under the encoder previously with the same codebook image as an initial image to be used at the decoder, the fractal coefficients are obtained through calculating the similarity between the codebook image and an input image to be encoded. As the decoding time could be remarkably reduced. For verifying the validity and universality of proposed method, We evaluated and analyzed the performance of decoding time and image quality for a number of still images and a moving picture with different distributed characteristics.

• Journal of IKEEE
• /
• v.9 no.1 s.16
• /
• pp.1-6
• /
• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.7C
• /
• pp.696-705
• /
• 2005

The rapid progress of the software has enabled individuals to copy and remake digital contents, which was only done by professionals. However, this rapid growth of software has brought many other defects. As a solution to the problems, contents producer needs to have certification and inspection of its contents text and hold the proprietary rights. In this paper, the new video watermarking scheme is proposed which is appropriate for the requirements mentioned for digital video contents and it is applied to MPEG-2 video encoder and decoder. In order to insert watermark sequence for digital video data, watermarking used blocks reordering algorithm and SCL(secret code list). It is satisfied two properties of cryptography that confidentiality and integrity. We test the proposed algorithm to see its performance in terms of watermark capacity, compression robustness and visual quality impact. According to the experiment of proposed watermarking algorithm, we obtained satisfactory results that watermark can still be extracted after MPEG-2 re-encoding at lower bit rates. It is important property for data hiding and user authentication in video data.