• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.3 s.309
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• pp.92-99
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure. Due to its efficient processing scheme, the proposed structure can be widely used in H.264 encoding and decoding SoC.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2473-2483
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• 2000

In this paper, The turbo code is used to effectively remove noise which is generated on the image communication channel. Turbo code had excellent decoding performance. However, it had limitations for real time communication because of the system complexity and time delay in decoding procedure. To overcome this problem, this paper proposed a new SRI(Semi Random Interleaved algorithm, which decrease the time delay, when the image data, which reduced the interleaver size of turbo code encoder and decoder, transmitted. The SRI algorithm was composed of 0.5 interleaver size from input frame sequence. When the data inputs in interleaver, the data recorded by row such as block interleaver. But, When the data read in interleaver, the data was read by randomly and the next data located by the just address simultaneously. Therefore, the SRI reduced half-complexity when it was compared with pre-existing method such as block, helical, random interleaver. The image data could be the real time processing when the SRI applied to turbo code.

• Journal of Communications and Networks
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• v.2 no.1
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• pp.76-84
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• 2000

Communication systems, including cell-based mobile communication systems, multiple satellite communication systems of multi-beam satellite systems, require reliable handoff methods between cell-to-cell, satellite-to-satellite of beam-to-team, respectively. Recent measurement of a CDMA cellular system indicates that the system is in handoff at about 35% to 70% of an average call period. Therefore, system reliability during handoff is one of the major system performance parameters and eventually becomes a factor in the overall system capacity. This paper presents novel and improved techniques for handoff in cellular communications, multi-beam and multi-satellite systems that require handoff during a session. this new handoff system combines the soft handoff mechanism currently implemented in the IS-95 CDMA with code and packet diversity combining techniques and an iterative decoding algorithm (Turbo Coding). the Turbo code introduced by Berrou et all. has been demonstrated its remarkable performance achieving the near Shannon channel capacity [1]. Recently. Turbo codes have been adapted as the coding scheme for the data transmission of the third generation international cellular communication standards : UTRA and CDMA 2000. Our proposed encoder and decoder schemes modified from the original Turbo code is suitable for the code and packet diversity combining techniques. this proposed system provides not only an unprecedented coding gain from the Turbo code and it iterative decoding, but also gain induced by the code and packet diversity combining technique which is similar to the hybrid Type II ARQ. We demonstrate performance improvements in AWGN channel and Rayleigh fading channel with perfect channel state information (CSI) through simulations for at low signal to noise ratio and analysis using exact upper bounding techniques for medium to high signal to noise ratio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of IKEEE
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• v.23 no.4
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• pp.1250-1256
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• 2019

Although one can easily generate real-world 3D mesh data using a 3D printer or a depth camera, the generated data inevitably includes unnecessary noise. Therefore, mesh denoising is essential to obtain intact 3D mesh data. However, conventional mathematical denoising methods require preprocessing and often eliminate some important features of the 3D mesh. To address this problem, this paper proposes a deep learning based 3D mesh denoising method. Specifically, we propose a convolution-based autoencoder model consisting of an encoder and a decoder. The convolution operation applied to the mesh data performs denoising considering the relationship between each vertex constituting the mesh data and the surrounding vertices. When the convolution is completed, a sampling operation is performed to improve the learning speed. Experimental results show that the proposed autoencoder model produces faster and higher quality denoised data than the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.4
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• pp.214-221
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• 2003

This paper shows an implementation of video codec (coder/decoder) on an embedded system. The video codec supports both H.261 and H.263 standards. For efficient real-time processing, the video codec is partitioned into a software module and a hardware module. Both modules are codesigned on an embedded system. The software module is processed on a real-time operating system and a RISC processor. It cooperates with the hardware module to compress and decompress images in real time. AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus) is used as the system bus. The hardware module works both as AHB masters and as AHB slaves. The encoder part of the hardware module operates in a pipelines mode to compress images in real time. The video codec compresses 15 CIF frames and simultaneously decompresses 15 CIF frames in a second according to H.261 or H.263 standard at 33 MHz frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.23-30
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• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.793-796
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• 2011

H.264/AVC compresses video data by applying DCT transform, quantization and entropy coding processes to the residual signal obtained by inter/intra prediction. This paper proposes a method enhancing an existing DC offset adjustment technology which uses information of neighboring blocks to reduce residual information for improving coding efficiency. DC offset information is not sent over bitstreams, but calculated in the same way both in the decoder and in the encoder. Experimental results show that the proposed method enhances coding efficiency by 0.25% in average BD-Rate compared to H.264/AVC and gives better or worse coding efficiency compared to the existing DC offset method depending on video sequences with coding efficiency degradation by 0.09% in average BD-Rate. This experimental results also show that further coding efficiency improvement is possible by applying the proposed method adaptively to slice or macroblock coding units.

• The Journal of the Korea Contents Association
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• v.12 no.12
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• pp.14-24
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• 2012

DVC (Distributed Video Coding) techniques need feedback channel for parity bit control to achieve the good RD performances, however, this causes the DVC system to have high decoding latency. In order to implement in real time environments and to accelerate commercializations, many research works have been focusing on the development of fast video decoding algorithm. As one of the real time implementations, this paper deals with a novel DVC scheme suitable for some application areas where source statistics such as motion information can be provided to the encoder side from the decoder side. That is, this paper propose a fast distributed video decoding scheme to improve the decoding speed by using the feedback of motion information derived in SI generation. Through computer simulations, it is shown that the proposed method outperforms the conventional fast DVC decoding schemes.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.13-18
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• 2015

The mutilevel holographic data storage offers considerable advantage for capacity, since it can store more than one bit per pixel. In this paper, we search the number of codewords for each code depending on three conditions: (1) the number of levels, (2) the number of pixels in a codeword, and (3) the minimum Euclidean distance of a code. Increasing the number of levels per pixel creates more capacity, while causing more errors, by reducing the noise margin. Increasing the number of pixels in a codeword can increase the code rate, which means more capacity, but increases the complexity of the encoder/decoder of the code. Increasing the minimum distance of a code reduces the detection error, while reducing the code rate of the code. In such a fashion, a system design will always have pros and cons, but our task is to find out an effective one under the given conditions for the system requirements. Therefore, the numbers we searched can provide some guidelines for effective code design.