• Journal of Broadcast Engineering
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• v.15 no.1
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• pp.52-62
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• 2010

Recently, DVC (Distributed Video Coding) is attracting a lot of research works since this enables us to implement a light-weight video encoder by distributing the high complex tasks such as motion estimation into the decoder side. In order to improve the coding efficiency of the DVC, the existing works have been focused on the efficient generation of side information (SI) or the virtual channel modeling which can describe the statistical channel noise well. But, in order to improve the overall performance, this paper proposes a new scheme that can be implemented with simple bit operations without introducing complex operation. That is, the performance of the proposed scheme is enhanced by using the fact that the Wyner-Ziv (WZ) frame and side information are highly correlated, and by reducing the effect of virtual channel noise which tends to be clustered in some regions. For this aim, this paper proposes an efficient pixel-domain WZ (PDWZ) CODEC which effectively exploits the statistical redundancy by using the code conversion and Gray code, and then reduces the channel noise by using the bit interleaver. Through computer simulations, it is shown that the proposed scheme can improve the performance up to 0.5 dB in objective visual quality.

• Journal of Broadcast Engineering
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• v.27 no.1
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• pp.31-43
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• 2022

Traditional video compression has developed so far based on hybrid compression methods through motion prediction, residual coding, and quantization. With the rapid development of technology through artificial neural networks in recent years, research on image compression and video compression based on artificial neural networks is also progressing rapidly, showing competitiveness compared to the performance of traditional video compression codecs. In this paper, a new method capable of improving the performance of such an artificial neural network-based video compression model is presented. Basically, we take the rate-distortion optimization method using the auto-encoder and entropy model adopted by the existing learned video compression model and shifts some components of the latent information that are difficult for entropy model to estimate when transmitting compressed latent representation to the decoder side from the encoder side, and finally compensates the distortion of lost information. In this way, the existing neural network based video compression framework, MFVC (Motion Free Video Compression) is improved and the BDBR (Bjøntegaard Delta-Rate) calculated based on H.264 is nearly twice the amount of bits (-27%) of MFVC (-14%). The proposed method has the advantage of being widely applicable to neural network based image or video compression technologies, not only to MFVC, but also to models using latent information and entropy model.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.687-698
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• 2014

ATSC is currently working on standardization of hybrid 3DTV broadcasting service in heterogenous network environment after completion of service-compatible 3DTV broadcasting service standard based on broadcasting channel. This paper proposes a convergence 3D video broadcasting method on broadcasting and IP network while guaranteeing a Full-HD 3D quality without degrading the image quality of legacy DTV. Specifically, this paper describes transmission of the 3D additional video using the ISO/IEC 23009-1 DASH, robust synchronization method under heterogenous network environments and system target decoder model for hybrid 3DTV receiver. Based on experimental results, we confirm that proposed technologies can be used as a core technology in the hybrid 3DTV standardization and a reference model for a development of hybrid 3DTV encoder and receiver.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.25-32
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• 2004

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In traffic field, the development of image using system is interesting issue. Because it has the advantage of price of installation and it does not obstruct traffic during the installation. In this study, 1 propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system interface of external environment, and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, Image classification and memory control of using FPGA, control of mouse signal. And finally, for stable operation of host controller board, uC/OS-II operating system is ported on the board.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.4
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• pp.1594-1617
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• 2018

In this paper, we consider a spectrum access scenario which consists of two groups of users, namely Primary Users (PUs) and Secondary Users (SUs) in Cooperative Cognitive Radio Networks (CCRNs). SUs cooperatively relay PUs messages based on Amplify-and-Forward (AF) and Decode-and-Forward (DF) cooperative techniques, in exchange for accessing some of the spectrum for their secondary communications. From the literatures, we found that the Conventional Distributed Algorithm (CDA) and Pragmatic Distributed Algorithm (PDA) aim to maximize the PU sum-rate resulting in a lower sum-rate for the SU. In this contribution, we have investigated a suit of distributed matching algorithms. More specifically, we investigated SU-based CDA (CDA-SU) and SU-based PDA (PDA-SU) that maximize the SU sum-rate. We have also proposed the All User-based PDA (PDA-ALL), for maximizing the sum-rates of both PU and SU groups. A comparative study of CDA, PDA, CDA-SU, PDA-SU and PDA-ALL is conducted, and the strength of each scheme is highlighted. Different schemes may be suitable for different applications. All schemes are investigated under the idealistic scenario involving perfect coding and perfect modulation, as well as under practical scenario involving actual coding and actual modulation. Explicitly, our practical scenario considers the adaptive coded modulation based DF schemes for transmission flexibility and efficiency. More specifically, we have considered the Self-Concatenated Convolutional Code (SECCC), which exhibits low complexity, since it invokes only a single encoder and a single decoder. Furthermore, puncturing has been employed for enhancing the bandwidth efficiency of SECCC. As another enhancement, physical layer security has been applied to our system by introducing a unique Advanced Encryption Standard (AES) based puncturing to our SECCC scheme.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.3
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• pp.19-27
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• 2001

Accordingly it is very important to not only develop the stack of protocol, but also try an international standardization regarding the standard protocol of VoIP. Has compared to the advanced countries having already some success in commercialization, Korea is relatively much less involved in relation to this technology and endeavors. In this regards, this paper is focused on developing a protocol stack made with encoder/decoder, the generator or the header file, syntax analyzer etc. based on the protocol grammars of Session Description Protocol supported by IETF RFC2327. For the sake of it, first describe the SDP BNF grammar based on IETF RFC2327 Augmented BNF. And then we produce the Abstract Syntax Tree, header file generator for encoding/decoding as applying the method of syntax directed to SDP protocol grammar.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.6 s.312
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• pp.60-70
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• 2006

Currently, Scalable Video Coding (SVC) is being standardized. By using scalability of SVC, QoS managed video streaming service is enabled in heterogeneous networks even with only one original bitstream. But current SVC is insufficient to dynamic video conversion for the scalability, thereby the adaptation of bitrate to meet a fluctuating network condition is limited. In this paper, we propose dynamic full-scalability conversion method for QoS adaptive video streaming in H.264/AVC SVC. To accomplish full scalability dynamic conversion, we propose corresponding bitstream extraction, encoding and decoding schemes. On the encoder, we newly insert the IDR NAL to solve the problems of spatial scalability conversion. On the extractor, we analyze the SVC bitstream to get the information which enable dynamic extraction. By using this information, real time extraction is achieved. Finally, we develop the decoder so that it can manage changing bitrate to support real time full-scalability. The experimental results showed that dynamic full-scalability conversion was verified and it was necessary for time varying network condition.

• Journal of Broadcast Engineering
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• v.9 no.3
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• pp.196-206
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• 2004

This paper presents an efficient joint disparity-motion estimation algorithm for stereo sequence CODEC. Disparity vectors are estimated by the left and right motion vectors and previous disparity vectors for every frame. In order to obtain more accurate disparity vectors. we include a spatial prediction Process after the feint estimation. From joint estimation and spatial prediction, we can obtain accurate disparity vectors and then Increase coding efficiency. Finally, we proposed the backward quadtree decomposition. which helps the encoder to have a more detailed disparity vector map without transmitting additional coding bits for quadtree information. We confirmed superior performance of the proposed method through computer simulation.