• Title/Summary/Keyword: encoder- decoder

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A Real Time 6 DoF Spatial Audio Rendering System based on MPEG-I AEP (MPEG-I AEP 기반 실시간 6 자유도 공간음향 렌더링 시스템)

  • Kyeongok Kang;Jae-hyoun Yoo;Daeyoung Jang;Yong Ju Lee;Taejin Lee
    • Journal of Broadcast Engineering
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    • v.28 no.2
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    • pp.213-229
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    • 2023
  • In this paper, we introduce a spatial sound rendering system that provides 6DoF spatial sound in real time in response to the movement of a listener located in a virtual environment. This system was implemented using MPEG-I AEP as a development environment for the CfP response of MPEG-I Immersive Audio and consists of an encoder and a renderer including a decoder. The encoder serves to offline encode metadata such as the spatial audio parameters of the virtual space scene included in EIF and the directivity information of the sound source provided in the SOFA file and deliver them to the bitstream. The renderer receives the transmitted bitstream and performs 6DoF spatial sound rendering in real time according to the position of the listener. The main spatial sound processing technologies applied to the rendering system include sound source effect and obstacle effect, and other ones for the system processing include Doppler effect, sound field effect and etc. The results of self-subjective evaluation of the developed system are introduced.

Hardware Implementation of Integer Transform and Quantization for H.264 (하드웨어 기반의 H.264 정수 변환 및 양자화 구현)

  • 임영훈;정용진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.12C
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    • pp.1182-1191
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    • 2003
  • In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

Audio Signal Coding Using Wavelet Transform (웨이블렛 변환을 이용한 오디오 코딩)

  • Bae, Seok-Mo;Kim, Do-Hyoung;Chung, Jae-Ho
    • The Journal of the Acoustical Society of Korea
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    • v.16 no.4
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    • pp.64-70
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    • 1997
  • This paper is aimed to propose a new wavelet audio signal coding scheme which reduces the complexity of well-known MPEG(Moving Picture Expert Group)-Audio. The filters of MPEG0audio apply subband technique on the 16-bits PCM audio to aquire bitstream of subband sample using dynamic bit allocation. If we use the wavelet coefficients instead of subband samples and 6 bands which is less than 32 bands of MPEG-audio, the complexity can be reduced. A new audio signal compression algorithm in this paper is based on wavelet transform and the proposed algorithm is compared with MPEG-audio. At the bitrate of 256kbps, the proposed algorithm maintains the CD(Compact-disc) quality. We were able to reduce the about 40% of complexity at encoder and about 70% at decoder.

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A Variable Data Rate Speech Coding Technique Based on the Inflection Point Detection of Speech (음성의 변곡점 추출 및 전송에 기반한 가변 데이터율 음성 부호화 기법)

  • Iem, Byeong-Gwan
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.4
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    • pp.562-565
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    • 2013
  • A new variable rate speech coding technique is proposed. The method is based on the observation that the speech signal approximately looks linear for a very short period of time. The information transmitted is the location and data value of inflection points. If the distance between the inflection points is large, the mid point location and its data value are also delivered. Thus, the encoder transmits both the location and the data value for the inflection samples, but the location only for the non-inflection points. The location information is expressed using one bit for each sample, 0 for non-inflection and 1 for inflection point. At the receiver, using the interpolation, the decoder estimates the untransmitted sample values for non-inflection locations from the received sample values for the inflection samples. With 50 % of computational cost of the existing CVSD delta modulation, the proposed method is expected to achieve the data rate of 36 to 38 kbps and the SNR of 10 to 13 dB.

Implementation of Fuzzy Self-Tuning PID and Feed-Forward Design for High-Performance Motion Control System

  • Thinh, Ngo Ha Quang;Kim, Won-Ho
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.14 no.2
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    • pp.136-144
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    • 2014
  • The existing conventional motion controller does not perform well in the presence of nonlinear properties, uncertain factors, and servo lag phenomena of industrial actuators. Hence, a feasible and effective fuzzy self-tuning proportional integral derivative (PID) and feed-forward control scheme is introduced to overcome these problems. In this design, a fuzzy tuner is used to tune the PID parameters resulting in the rejection of the disturbance, which achieves better performance. Then, both velocity and acceleration feed-forward units are added to considerably reduce the tracking error due to servo lag. To verify the capability and effectiveness of the proposed control scheme, the hardware configuration includes digital signal processing (DSP) which plays the main role, dual-port RAM (DPRAM) to guarantee rapid and reliable communication with the host, field-programmable gate array (FPGA) to handle the task of the address decoder and receive the feed-back encoder signal, and several peripheral logic circuits. The results from the experiments show that the proposed motion controller has a smooth profile, with high tracking precision and real-time performance, which are applicable in various manufacturing fields.

Analysis of Power Saving Factor for a DVS Based Multimedia Processor (DVS 기반 멀티미디어 프로세서의 전력절감율 분석)

  • Kim Byoung-Il;Chang Tae-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.1
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    • pp.95-100
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    • 2005
  • This paper proposes a DVS method which effectively reduces the power consumption of multimedia signal processor. Analytic derivations of effective range of its power saving factor are obtained with the assumption of a Gaussian distribution for the frame-based computational burden of the multimedia processor. A closed form equation of the power saving factor is derived in terms of the mean-standard deviation of the distribution. An MPEG-2 video decoder algorithm and AAC encoder algorithm are tested on ARM9 RISC processor for the experimental verification of the power saying of the proposed DVS approach. The experimental results with diverse MPEG-2 video and audio files show 50~30% power saving factor and show good agreement with those of the analytically derived values.

Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems

  • Oh, Myeong-Hoon;Kim, Young Woo;Kim, Hag Young;Kim, Young-Kyun;Kim, Jin-Sung
    • ETRI Journal
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    • v.39 no.4
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    • pp.582-591
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    • 2017
  • To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

Real-Time DSP Implementation of Adaptive Multi-Rate with TMS320C542 board (TMS320C542보드를 이용한 Adaptive Multi-Rate 음성부호화기의 실시간 구현)

  • 박세익;전라온;이인성
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.827-830
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    • 2000
  • 3GPP and ETSI adopted AMR(Adaptive Multi-Rate) as a standard for next generation IMT-2000 service. In this paper, we analyzed algorithm about AMR and optimized ANSI C source on the C complier and assembly language of Texas Instrument . The implemented AMR speech codec requires 28.2MIPS of complexity for encoder and 5.5MIPS for decoder. we performed real-time implementation of AMR speech codec using 82% of TMS320C5402 with 40 MIPS specification. We give proof that the output speech of the implemented speech codec on DSP board is identical with result of C source program simulation. Also the reconstructed speech is verified in the real-time environment consisted of microphone and speaker.

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Side Information Extrapolation Using Motion-aligned Auto Regressive Model for Compressed Sensing based Wyner-Ziv Codec

  • Li, Ran;Gan, Zongliang;Cui, Ziguan;Wu, Minghu;Zhu, Xiuchang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.2
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    • pp.366-385
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    • 2013
  • In this paper, we propose a compressed sensing (CS) based Wyner-Ziv (WZ) codec using motion-aligned auto regressive model (MAAR) based side information (SI) extrapolation to improve the compression performance of low-delay distributed video coding (DVC). In the CS based WZ codec, the WZ frame is divided into small blocks and CS measurements of each block are acquired at the encoder, and a specific CS reconstruction algorithm is proposed to correct errors in the SI using CS measurements at the decoder. In order to generate high quality SI, a MAAR model is introduced to improve the inaccurate motion field in auto regressive (AR) model, and the Tikhonov regularization on MAAR coefficients and overlapped block based interpolation are performed to reduce block effects and errors from over-fitting. Simulation experiments show that our proposed CS based WZ codec associated with MAAR based SI generation achieves better results compared to other SI extrapolation methods.

Improvement of Overlapped Codebook Search in QCELP (QCELP에서 중첩된 코드북 검색의 개선)

  • 박광철;한승진;이정현
    • The KIPS Transactions:PartC
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    • v.8C no.1
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    • pp.105-112
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    • 2001
  • In this paper, we present the advanced QCELP codebook search improving the qualification of speech, which can make QCELP vocoder used in noise robust system. While conventional QCELP usually searches stochastic codebook once, we can find that two times search is the most suitable for improving the quality of speech after we did 2-5 times search. Consequently, the advanced QCELP vocoder represents excitation signal in detail using two times precise quantization and so improve the qualification of speech. In our experiment, we use the speeches collected from circumstance (such as lecture room, house, street, laboratory etc.) without regarding noise as input dat and measure the speech Qualification using SNR, segSNR. As the result of the experiment, we find that the advanced QCELP makes SNR and segSNR improved by 38.35% and 65.51% respectively compared with conventional QCELP.

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