• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.7
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• pp.37-42
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• 2008

In this paper, a real-time multiview video coding system using fast disparity estimation is proposed. In the multiview encoder, adaptive disparity-motion estimation (DME) for an effective 3-dimensional (3D) processing are proposed. That is, by adaptively predicting the mutual correlation between stereo images in the key-frame using the proposed algorithm, the bandwidth of stereo input images can be compressed to the level of a conventional 2D image and a predicted image also can be effectively reconstructed using a reference image and adaptive disparity vectors. Also, in multiview decoder, intermediate view reconstruction (IVR) using adaptive disparity search algorithm (DSA) for real-time multiview video processing is proposed. The proposed IVR can reduce a processing time of disparity estimation by selecting adaptively disparity search range. Accordingly, the proposed multiview video coding system is able to increase the efficiency of the coding rate and improve the resolution.

• Journal of Multimedia Information System
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• v.4 no.1
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• pp.19-26
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• 2017

The compression of video for both full HD and UHD requires the inclusion of extra vertical lines to every video frame, named as the DTV essential hidden area (DEHA), for the effective functioning of the MPEG-2/4/H encoder, stream, and decoder. However, while the encoding/decoding process is dependent on the DEHA, the DEHA is conventionally viewed as a redundancy in terms of channel utilization or storage efficiency. This paper proposes a block mode DEHA method to more effectively utilize the DEHA. Partitioning video block images and then evenly filling the representative DEHA macroblocks with the average DC coefficient of the active video macroblock can minimize the amount of DEHA data entering the compressed video stream. Theoretically, this process results in smaller DEHA data entering the video stream. Experimental testing of the proposed block mode DEHA method revealed a slight improvement in the quality of the active video. Outside of this technological improvement to video quality, the attractiveness of the proposed DEHA method is also heightened by the ease that it can be implemented with existing video encoders.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.745-747
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• 1999

디지털 TV의 동영상 표준인 MPEG2는 방대한 양의 디지털 데이터를 발생한다. 그러나 현재 사용하고 있는 디지털 저장 매체의 수용 능력에는 한계가 있으므로 저장을 위해 전송된 high bit rate의 MPEG2 bitstream을 더욱 낮은 bit rate의 bitstream으로 전환하는 transcoding 기법이 반드시 필요하다. 기존의 encoder와 decoder를 이용하여 구현 가능한 장점이 있는 cascade transcoder는 reencoding시 motion estimation에 많은 수행 시간이 소요되므로, motion estimation 과정을 최소화하면서 optimal motion vector를 구할 수 있는 motion vector refinement 기법을 MPEG2 cascade transcoder에 적용하였다. 결과 처리 속도는 3-5배 향상되었고 화질은 기존의 72 transcoder에 비해 평균 0.1dB 이상의 FSNR 향상이 있었다. 또한 1Mbps와 같은 low bit rate에서 더욱 큰 화질 향상이 있었다.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2023-2024
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• 2006

1962년 Gallager에 의해 처음 제안된 LDPC 부호는 복호를 수행하는 부호방식으로 패리티 행렬(H)의 대부분이 0으로 구성되어 복호시에 적은 연산량을 요구하며, shannon의 한계에 도달하는 복호 능력으로, 차세대 통신의 주된 부호 방식으로 고려되고 있다. 하지만, LDPC는 부호화에 있어서 여타 다른 부호방식에 비해 복잡한 특성을 가지고 있으므로, 이를 개선하기 위한 부호방식의 적용이 필요하다. 본 논문에서는 효율 적인 부호화를 위하여 Dual-diagonal H parity행렬을 구성 하고, 쉽게 부호 길이를 확장 할 수 있는 Quasi-Cyclic 방식을 적용한 복호기를 구현하였다.

• Annual Conference on Human and Language Technology
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• 2018.10a
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• pp.470-473
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• 2018

최근 제안된 순환 신경망 기반 Encoder-Decoder 모델은 기계번역에서 좋은 성능을 보인다. 하지만 이는 대량의 병렬 코퍼스를 전제로 하며 병렬 코퍼스가 소량일 경우 데이터 희소성 문제가 발생하며 번역의 품질은 다소 제한적이다. 본 논문에서는 기계번역의 이러한 문제를 해결하기 위하여 단일-언어(Monolingual) 데이터를 학습과정에 사용하였다. 즉, 역-번역(Back-translation)을 이용하여 단일-언어 데이터를 가상 병렬(Pseudo Parallel) 데이터로 변환하는 방식으로 기존 병렬 코퍼스를 확장하여 번역 모델을 학습시켰다. 역-번역 방법을 이용하여 영-한 번역 실험을 수행한 결과 +0.48 BLEU 점수의 성능 향상을 보였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.672-683
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• 1990

The line code for ISDN subscriber loops is a critical choice in designing U-interface transceiver, since it affects system performance in a crucial way. This paper provides the performance analysis of U-interface transceiver systems employing four different line codes AMI, MMS43, VMDB5, and 2B1Q. The codes are compared using computer simulation studies, and three performance parameters of the four codes such as power spectrum, eye width, and error probability are used for the comparison. The simulation model consists of the encoder, transmit filter (root-raised cosine filter), channel, receive filter, zero-forcing equalizer, sampler, and decoder. The near-end crosstalk and addive white gaussian noise are considered as teh principal impediments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.17-17
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• 2001

본 논문은 0.6㎛ CMOS 기술로 LZSS 알고리즘과 엔트로피 부호를 이용한 부호기/복호기 단일-칩의 본 논문은 0.6uul CMOS 기술로 LZSS 알고리즘과 엔트로피 부호를 이용한 부호기/복호기 단일-칩의 VLSI 설계 및 구현에 관하여 기술하였다. 처리 속도 50MHz를 갖는 사전탐색처리장치(DISP)의 메모리는 2K×Bbit 크기를 사용하였다. 이것은 매번 33개 클럭 중 한 개의 클럭은 사전의 WINDOW 배열을 갱신으로 사용하고 나머지 클럭은 주기마다 한 개의 데이터 기호를 바이트 단위로 압축을 실행한다. 결과적으로, LZSS 부호어 출력에 엔트로피 부호를 적용하여 46%의 평균 압축률을 보였다. 이것은 LZSS에 보다 7% 정도의 압축 성능이 향상된 것이다.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.201-203
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• 2005

The best method to study language is to talking with a native speaker. A voice recognition technology can be used to develope a language study machine. SD(Speaker dependant) and SI(speaker independant) voice recognition method is used for the language study machine. MP3 Player. FM Radio. Alarm clock functions are added to enhance the value of the product. The machine is designed with a DSP(Digital Signal Processing) chip for voice recognition. MP3 encoder/decoder chip. FM tumer and SD flash memory card. This paper deals with the application of SD ad SD voice recognition. flash memory file system. PC download function using USB ports, English conversation text function by the use of SD flash memory. LCD display control. MP3 encoding and decoding, etc. The study contents are saved in SD flash memory. This machine can be helpful from child to adult by changing the SD flash memory.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.241-244
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• 2003

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In this study, I propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system, interface of external environment. and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, image classification and memory control of using FPGA, control of mouse signal. And finally, fer stable operation of host controller board, uC/OS-II operating system is ported on the board.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.