• Title/Summary/Keyword: encoder- decoder

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A study on Korean multi-turn response generation using generative and retrieval model (생성 모델과 검색 모델을 이용한 한국어 멀티턴 응답 생성 연구)

  • Lee, Hodong;Lee, Jongmin;Seo, Jaehyung;Jang, Yoonna;Lim, Heuiseok
    • Journal of the Korea Convergence Society
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    • v.13 no.1
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    • pp.13-21
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    • 2022
  • Recent deep learning-based research shows excellent performance in most natural language processing (NLP) fields with pre-trained language models. In particular, the auto-encoder-based language model proves its excellent performance and usefulness in various fields of Korean language understanding. However, the decoder-based Korean generative model even suffers from generating simple sentences. Also, there is few detailed research and data for the field of conversation where generative models are most commonly utilized. Therefore, this paper constructs multi-turn dialogue data for a Korean generative model. In addition, we compare and analyze the performance by improving the dialogue ability of the generative model through transfer learning. In addition, we propose a method of supplementing the insufficient dialogue generation ability of the model by extracting recommended response candidates from external knowledge information through a retrival model.

A study on the Encoding Method for High Performance Moving Picture Encoder (고속 동영상 부호기를 위한 부호화 방법에 관한 연구)

  • 김용욱;허도근
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.2
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    • pp.352-358
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    • 2004
  • This paper is studied the improvement of performance for moving picture encoder using H.263. This is used the new motion vector search algorithm using a relation with neighborhood search point and is applied the integer DCT for the encoder. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer Dn can reduce the operation amount than basis DCT with having an equal PSNR. The new motion vector search algorithm is showed almost similar PSNR as reducing the operation amount than the conventional motion vector search algorithm. To experiment a compatibility of the integer DCT and the conventional DCT, according to result compare case that uses a method only and case that uses the alternate two methods of the integer DCT or the conventional DCT to H.263 encoder and decoder, case that uses the alternate two methods is showed doing not deteriorate PSNR-and being each other compatible visually than case that uses an equal method only.

Fast Mode Decision for MPEG-2 to H.264 Transcoding (MPEG-2에서 H.264로 변환하기 위한 고속 모드 결정 기법)

  • Kim, Won-Kyun;Park, Kyung-Jun;You, Jong-Min;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3C
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    • pp.269-277
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    • 2007
  • In this paper, we present a efficient transcoding method from MPEG-2 to H.264. The proposed transcoder is the transcoding method for spatial domain which consists of MPEG-2 decoder part and H.264 encoding part. In transcoder, we can get useful information to estimate less probable modes from MPEG-2 decoder. Using this information, H.264 encoder chooses the macroblock mode of I-frame and P-frame adaptively to reduce the whole complexity of the transcoder. Our experimental result shows that the proposed algorithm can archive about $30\sim60%$ computational saving without significant degradation of visual quality and increasing of bit rate.

Design of a Full-Adder Using Current-Mode Multiple-Valued Logic CMOS Circuits (전류 모드 다치 논리 CMOS 회로를 이용한 전가산기 설계)

  • Lee, Yong-Seop;Gwak, Cheol-Ho;Kim, Jeong-Beom
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.1
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    • pp.76-82
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    • 2002
  • This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

SELECTIVE HASH-BASED WYNER-ZIV VIDEO CODING

  • Do, Tae-Won;Shim, Hiuk-Jae;Ko, Bong-Hyuck;Jeon, Byeung-Woo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2009.01a
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    • pp.351-354
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    • 2009
  • Distributed video coding (DVC) is a new coding paradigm that enables to exploit the statistics among sources only in decoder and to achieve extremely low complex video encoding without any loss of coding efficiency. Wyner-Ziv coding, a particular implementation of DVC, reconstructs video by correcting noise on side information using channel code. Since a good quality of side information brings less noise to be removed by the channel code, generation of good side information is very important for the overall coding efficiency. However, if there are complex motions among frames, it is very hard to generate a good quality of side information without any information of original frame. In this paper, we propose a method to enhance the quality of the side information using small amount of additional information of original frame in the form of hash. By decoder's informing encoder where the hash has to be transmitted, side information can be improved enormously with only small amount of hash data. Therefore, the proposed method gains considerable coding efficiency. Results of our experiment have verified average PSNR gain up to 1 dB, when compared to the well-known DVC codec, known as DISCOVER codec.

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A Study on East Fractal Image Decoder Using a Codebook Image (코드북 영상을 이용한 고속 프랙탈 영상 복호기에 관한 연구)

  • 이기욱;곽노윤
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.4 no.4
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    • pp.434-440
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    • 2003
  • Since Jacquine introduced the image coding algorithm using fractal theory, many fractal image compression algorithms providing good quality at low bit rate have been proposed by Fisher and Beaumount et al.. But a problem of the previous implementations is that the decoding rests on an iterative procedure whose complexity is image-dependent. This paper proposes an iterative-free fractal image decoding algorithm to reduce the decoding time. In the proposed method, under the encoder previously with the same codebook image as an initial image to be used at the decoder, the fractal coefficients are obtained through calculating the similarity between the codebook image and an input image to be encoded. As the decoding process can be completed with received fractal coefficients and predefined initial image without repeated iterations, the decoding time could be remarkably reduced.

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Design and Implementation of the 155Mbps Adaptive CODEC for Ka-band Satellite Communications

  • Park, Eun-A;Chang, Dae-Ig;Kim, Nae-Soo
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1940-1943
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    • 2002
  • In this paper, we presented the design and implementation of 155Mbps satellite Modem adaptively compensated against the rain attenuation. In order to compensate the rain attenuation over high-speed satellite ink, the adaptive coding schemes with variable coding rates and the pragmatic TCM that can be decoded both the QPSK and TC-8PSK using same Viterbi decoder was studied and analyzed. The pragmatic TCM with rate 213, selected to the optimal parameters for implementation, was modeled by VHDL in this paper. The key design issues are how to achieve a high data rate and how to integrated into a single ASIC chip various functions such as the different data rates, Scrambler/descrambler, Interleaver, Encoder/decoder, and BPSK/QPSK/8PSK modulator/demodulator. The implemented 155M0ps adaptive MODEM has the simplified interface circuits among the many functional blocks, and parallel processing architecture to achieve the high data rate. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the 0.25 $\mu\textrm{m}$ CMOS standard cell technology.

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8 Antenna Polar Switching Up-Down Relay Networks

  • Li, Jun;Lee, Moon-Ho;Yan, Yier;Peng, Bu Shi;Hwang, Gun-Joon
    • Journal of electromagnetic engineering and science
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    • v.11 no.4
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    • pp.239-249
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    • 2011
  • In this paper, we propose a reliable $8{\times}8$ up-down switching polar relay code based on 3GPP LTE standard, motivated by 3GPP LTE down link, which is 30 bps/Hz for $8{\times}8$ MIMO antennas, and by Arikan's channel polarization for the frequency selective fading (FSF) channels with the generator matrix $Q_8$. In this scheme, a polar encoder and OFDM modulator are implemented sequentially at both the source node and relay nodes, the time reversion and complex conjugation operations are separately implemented at each relay node, and the successive interference cancellation (SIC) decoder, together with the cyclic prefix (CP) removal, is performed at the destination node. Use of the scheme shows that decoding at the relay without any delay is not required, which results in a lower complexity. The numerical result shows that the system coded by polar codes has better performance than currently used designs.

Complexity of Distributed Source Coding using LDPCA Codes (LDPCA 부호를 이용한 실용적 분산 소스 부호화의 복호복잡도)

  • Jang, Min;Kang, Jin-Whan;Kim, Sang-Hyo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.4C
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    • pp.329-336
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    • 2010
  • Distributed source coding (DSC) system moves computational burden from encoder to decoder, so it takes higher decoding complexity. This paper explores the problem of reducing the decoding complexity of practical Slepian-Wolf coding using low-density parity check accumulate (LDPCA) codes. It is shown that the convergence of mean magnitude (CMM) stopping criteria for LDPC codes help reduce the 85% of decoding complexity under the 2% of compression rate loss, and marginal initial rate request reduces complexity below complexity minimum bound. Moreover, inter-rate stopping criterion, modified for rate-adaptable characteristic, is proposed for LDPCA codes, and it makes decoder perform less iterative decoding than normal stopping criterion does when channel characteristic is unknown.

Hardware Implementation of Context Modeler in HEVC CABAC Decoder (HEVC CABAC 복호기의 문맥 모델러 설계)

  • Kim, Sohyun;Kim, Doohwan;Lee, Seongsoo
    • Journal of IKEEE
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    • v.21 no.3
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    • pp.280-283
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    • 2017
  • HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.