• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.736-745
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• 2002

In network delivery of compressed video, packets may be lost if the channel is unreliable like Internet. Such losses tend to of cur in burst like continuous bit-stream error. In this paper, we propose an effective error-concealment approach to which an error resilient video encoding approach is applied against burst errors and which reduces a complexity of error concealment at the decoder using data hiding. To improve the performance of error concealment, a temporal and spatial error resilient video encoding approach at encoder is developed to be robust against burst errors. For spatial area of error concealment, block shuffling scheme is introduced to isolate erroneous blocks caused by packet losses. For temporal area of error concealment, we embed parity bits in content data for motion vectors between intra frames or continuous inter frames and recovery loss packet with it at decoder after transmission While error concealment is performed on error blocks of video data at decoder, it is computationally costly to interpolate error video block using neighboring information. So, in this paper, a set of feature are extracted at the encoder and embedded imperceptibly into the original media. If some part of the media data is damaged during transmission, the embedded features can be extracted and used for recovery of lost data with bi-direction interpolation. The use of data hiding leads to reduced complexity at the decoder. Experimental results suggest that our approach can achieve a reasonable quality for packet loss up to 30% over a wide range of video materials.

• Journal of Broadcast Engineering
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• v.17 no.1
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• pp.179-190
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• 2012

In Distributed Video Coding(DVC), a low complexity encoder can be realized by shifting complex processes of encoder such as motion estimation to decoder. Since not only motion estimation/compensation processes but also channel decoding process needs to be performed at DVC decoder, the complexity of a decoder is significantly increased in consequence. Therefore, various fast channel decoding methods are proposed for the most computationally complex part, which is the channel decoding process in DVC decoding. As the channel decoding process becomes faster using various methods, however, the complexity of the other processes are relatively highlighted. For instance, the complexity of side information generation process in the DVC decoder is relatively increased. In this paper, therefore, a fast method for the DVC decoding is proposed by using adaptive search range method in side information generation process. Experimental results show that the proposed method achieves time saving of about 63% in side information generation process, while its rate distortion performance is degraded only by about 0.17% in BDBR.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.119-124
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• 2009

In this paper, AMR-WB+ audio coder is implemented, in real-time, using Intel 400MHz Xscale PXA250 with 32bit RISC processor ARM9E-J(R)core. The assembly code for ARM9E-J(R)core is developed through the serial process of C code optimization, cross compile, assembly code manual optimization and adjusting the optimized code to Embedded Visual C++ platform. C code is trimmed on Visual C++ platform. Cross compile and assembly code manual optimization are performed on CodeWarrior with ARM compiler. Through these stages the code for both ARM EVM board and PDA is implemented. The average complexities of the code are 160.75MHz on encoder and 33.05MHz on decoder. In case of static link library(SLL), the required memories are 65.21Kbyte, 32.01Kbyte and 279.81Kbyte on encoder, decoder and common sources, respectively. The implemented coder is evaluated using 16 test vectors given by 3GPP to verify the bit-exactness of the coder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.5
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• pp.209-217
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• 1985

Using the Reed-Muller Codes, the encoder and decoder system has been designed and tested in this paper. The error correcting capability of this code is [J/2} or less and the error correcting procedure can be implemented easily by using simple logic circuitry. The encoding and decoding circuits are obtained by the cyclic property and for the O15, 11) Reed-Muller code majority-logic decoding is taken. The performance is measured in error probability and weight destribution. The encoder and decoder system has been designed, implemented and interfaced with the microcomputer by using the 8255 chip. Experimental results show that the system has single error-correcting capability and total execution time for a data is about 70usec. When the probability of channel error is $10^{-6}$~$10^{-4}$ the system using the (15, 11) Reed-Muller code works very good.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.2
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• pp.195-199
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• 2010

(255,223) RS(Reed-Solomon) code which is the CCSDS(Consultative Committee for Space Data Systems) standard was used in the STSAT-3 to correct errors during the downlink of payload data. The RS encoder developed by VHDL was implemented in MMU(Mass Memory Unit). Moreover, the RS decoder developed by C-language was implemented in the DRS(Data Receiving System) of ground station. In this paper, we reported the design and analysis results of RS(255,223) for STSAT-3. The BER(Bit Error Rate) performance from MMU to DRS was confirmed through the downlink test at 16 Mbps. Also, the error correction performance and capability of RS(255,223) was tested by the manual attenuation of the RF(Radio Frequency) signal in the X-band transmitter resulting in putting some errors in the communication line.

• Journal of KIISE
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• v.44 no.8
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• pp.774-781
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• 2017

Mention detection systems use nouns or noun phrases as a head and construct a chunk of text that defines any meaning, including a modifier. The term "mention detection" relates to the extraction of mentions in a document. In the mentions, a coreference resolution pertains to finding out if various mentions have the same meaning to each other. A pointer network is a model based on a recurrent neural network (RNN) encoder-decoder, and outputs a list of elements that correspond to input sequence. In this paper, we propose the use of mention detection using pointer networks. Our proposed model can solve the problem of overlapped mention detection, an issue that could not be solved by sequence labeling when applying the pointer network to the mention detection. As a result of this experiment, performance of the proposed mention detection model showed an F1 of 80.07%, a 7.65%p higher than rule-based mention detection; a co-reference resolution performance using this mention detection model showed a CoNLL F1 of 52.67% (mention boundary), and a CoNLL F1 of 60.11% (head boundary) that is high, 7.68%p, or 1.5%p more than coreference resolution using rule-based mention detection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.103-113
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• 2001

This paper described a design and implementation of a single-chip encoder/decoder using the LZSS algorithm and entropy coding in 0.6${\mu}{\textrm}{m}$ CMOS technology. Dictionary storage for the dictionary search processor(DISP) used a 2K$\times$8bit on-chip memory with 50MHz clock speed. It performs compression on byte-oriented input data at a data rate of one byte per clock cycle except when one out of every 33 cycles is used to update the string window of dictionary. In result, the average compression ratio is 46% by applied entropy coding of the LZSS codeword output. This is to improved on the compression performance of 7% much more then LZSS.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• Journal of The Korean Association of Information Education
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• v.20 no.4
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• pp.333-340
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• 2016

When elementary students write their own sentences, it is often educationally beneficial to compare them with other people's similar sentences. However, it is impractical for use in most classrooms, because it is burdensome for teachers to look up all of the sentences written by students. To cope with this problem, we propose a novel approach for automatic selection of similar sentences based on a three-step process: 1) extracting the subword units from the word-level sentences, 2) training the model with the encoder-decoder architecture, and 3) using the approximate k-nearest neighbor search algorithm to find the similar sentences. Experimental results show that the proposed approach achieves the accuracy of 75% for our test data.