• Title/Summary/Keyword: embedded processors

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A LSB-based Efficient Selective Encryption of Fingerprint Images for Embedded Processors (임베디드 프로세서에 적합한 LSB 기반 지문영상의 효율적인 부분 암호화 방법)

  • Moon, Dae-Sung;Chung, Yong-Wha;Pan, Sung-Bum;Moon, Ki-Young;Kim, Ju-Man
    • Journal of Korea Multimedia Society
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    • v.9 no.10
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    • pp.1304-1313
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    • 2006
  • Biometric-based authentication can provide strong security guarantee about the identity of users. However, security of biometric data is particularly important as the compromise of the data will be permanent. In this paper, we propose a secure and efficient protocol to transmit fingerprint images from a fingerprint sensor to a client by exploiting characteristics of fingerprint images. Because the fingerprint sensor is computationally limited, however, such encryption algorithm may not be applied to the full fingerprint images in real-time. To reduce the computational workload on the resource-constrained sensor, we apply the encryption algorithm to a specific bitplane of each pixel of the fingerprint image. We use the LSB as specific bitplane instead of MSB used to encrypt general multimedia contents because simple attacks can reveal the fingerprint ridge information even from the MSB-based encryption. Based on the experimental results, our proposed algorithm can reduce the execution time of the full encryption by a factor of six and guarantee both the integrity and the confidentiality without any leakage of the ridge information.

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The Design and Simulation of Out-of-Order Execution Processor using Tomasulo Algorithm (토마술로 알고리즘을 이용하는 비순차실행 프로세서의 설계 및 모의실행)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.4
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    • pp.135-141
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    • 2020
  • Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

A Study of Air Pollution Monitoring System using Gossiping Route Protocol in wireless Sensor Network (Gossiping Route Protocol을 이용한 공기오염감지시스템에 관한 연구)

  • Park, Yong-Man;Kim, Hie-Sik;Kim, Gyu-Sik;Lee, Moon-Gyu;Ayurzana, Odgerel;Kwon, Jong-Won;Koo, Sang-Jun;Oh, Shi-Hwan;Kim, Dong-Ki;Jo, Ik-Kyun;Park, Jeong-Hun
    • Proceedings of the KIEE Conference
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    • 2007.10a
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    • pp.485-486
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    • 2007
  • Wireless Sensor Networking is state of the art technology that has a wide range of potential applications. Sensor network generally consists of a large number of distributed nodes that organize themselves into a multi-hop wireless network. Each node has one or more sensors, embedded processors and low-power radios, and is normally battery operated because of small size. In this paper wireless sensor networking technology applies to the environment monitoring system in the underground. This system can monitor a pollution level of the underground in realtime for keeping up a comfortable environment.

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The proposal of a cryptographic method for the communication message security of GCS to support safe UAV operations (안정적인 UAV 운영을 위한 GCS의 통신메시지의 암호화 제안)

  • Kim, Byoung-Kug;Hong, Sung-Hwa;Kang, Jiheon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.10
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    • pp.1353-1358
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    • 2021
  • IoT (Internet of Things) emerges from various technologies such as communications, micro processors and embedded system and so on. The IoT has also been used to UAV (Unmanned Aerial Vehicle) system. In manned aircraft, a pilot and co-pilot should control FCS (Flight Control System) with FBW(Fly By Wire) system for flight operation. In contrast, the flight operation in UAV system is remotely and fully managed by GCS (Ground Control System) almost in real time. To make it possible the communication channel should be necessary between the UAV and the GCS. There are many protocols between two systems. Amongst them, MAVLink (Macro Air Vehicle Link) protocol is representatively used due to its open architecture. MAVLink does not define any securities itself, which results in high vulnerability from external attacks. This paper proposes the method to enhance data security in GCS network by applying cryptographic methods to the MAVLink messages in order to support safe UAV operations.

Semantic Depth Data Transmission Reduction Techniques using Frame-to-Frame Masking Method for Light-weighted LiDAR Signal Processing Platform (LiDAR 신호처리 플랫폼을 위한 프레임 간 마스킹 기법 기반 유효 데이터 전송량 경량화 기법)

  • Chong, Taewon;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.12
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    • pp.1859-1867
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    • 2021
  • Multi LiDAR sensors are being mounted on autonomous vehicles, and a system to multi LiDAR sensors data is required. When sensors data is transmitted or processed to the main processor, a huge amount of data causes a load on the transport network or data processing. In order to minimize the number of load overhead into LiDAR sensor processors, only semantic data is transmitted through data comparison between frames in LiDAR data. When data from 4 LiDAR sensors are processed in a static environment without moving objects and a dynamic environment in which a person moves within sensor's field of view, in a static experiment environment, the transmitted data reduced by 89.5% from 232,104 to 26,110 bytes. In dynamic environment, it was possible to reduce the transmitted data by 88.1% to 29,179 bytes.

Image Contrast and Sunlight Readability Enhancement for Small-sized Mobile Display (소형 모바일 디스플레이의 영상 컨트라스트 및 야외시인성 개선 기법)

  • Chung, Jin-Young;Hossen, Monir;Choi, Woo-Young;Kim, Ki-Doo
    • Journal of IKEEE
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    • v.13 no.4
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    • pp.116-124
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    • 2009
  • Recently the CPU performance of modem chipsets or multimedia processors of mobile phone is as high as notebook PC. That is why mobile phone has been emerged as a leading ICON on the convergence of consumer electronics. The various applications of mobile phone such as DMB, digital camera, video telephony and internet full browsing are servicing to consumers. To meet all the demands the image quality has been increasingly important. Mobile phone is a portable device which is widely using in both the indoor and outside environments, so it is needed to be overcome to deteriorate image quality depending on environmental light source. Furthermore touch window is popular on the mobile display panel and it makes contrast loss because of low transmittance of ITO film. This paper presents the image enhancement algorithm to be embedded on image enhancement SoC. In contrast enhancement, we propose Clipped histogram stretching method to make it adaptive with the input images, while S-shape curve and gain/offset method for the static application And CIELCh color space is used to sunlight readability enhancement by controlling the lightness and chroma components which is depended on the sensing value of light sensor. Finally the performance of proposed algorithm is evaluated by using histogram, RGB pixel distribution, entropy and dynamic range of resultant images. We expect that the proposed algorithm is suitable for image enhancement of embedded SoC system which is applicable for the small-sized mobile display.

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Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design (소면적 32-bit 2/3단 파이프라인 프로세서 설계)

  • Lee, Kwang-Min;Park, Sungkyung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.59-67
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    • 2016
  • With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32=64$ multiplication, 64/32=32 division, $32{\times}32+64=64$ MAC (multiply and accumulate) operations together with 32*32=64 Galois field multiplication operation for encryption processing in wireless communications. It provides selective inclusion of these algebraic logic blocks if necessary in order to reduce the area of the overall processor. In this case, the gate count of our integer core amounts to 12k~22k and has a performance of 0.57 DMIPS/MHz and 1.024 Coremark/MHz.

Implementation of Pixel Subword Parallel Processing Instructions for Embedded Parallel Processors (임베디드 병렬 프로세서를 위한 픽셀 서브워드 병렬처리 명령어 구현)

  • Jung, Yong-Bum;Kim, Jong-Myon
    • The KIPS Transactions:PartA
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    • v.18A no.3
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    • pp.99-108
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    • 2011
  • Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of $2.3{\times}$ over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only $1.4{\times}$ over the same baseline SIMD array performance. In addition, the proposed instructions achieve $2.5{\times}$ better energy efficiency than the baseline program, while MMX-type instructions achieve only $1.8{\times}$ better energy efficiency than the baseline program.

Selective B Slice Skip Decoding for Complexity Scalable H.264/AVC Video Decoder (H.264/AVC 복호화기의 복잡도 감소를 위한 선택적 B 슬라이스 복호화 스킵 방법)

  • Lee, Ho-Young;Kim, Jae-Hwan;Jeon, Byeung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.48 no.3
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    • pp.79-89
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    • 2011
  • Recent development of embedded processors makes it possible to play back video contents in real-time on portable devices. Because of their limited battery capacity and low computational performance, however, portable devices still have significant problems in real-time decoding of high quality or high resolution compressed video. Although previous approaches are successful in achieving complexity-scalable decoder by controlling computational complexity of decoding elements, they cause significant objective quality loss coming from mismatch between encoder and decoder. In this paper, we propose a selective B slice skip-decoding method to implement a low complexity video decoder. The proposed method performs selective skip decoding process of B slice which satisfies the proposed conditions. The skipped slices are reconstructed by simple reconstruction method utilizing adjacent reconstructed pictures. Experimental result shows that proposed method not only reduces computational complexity but also maintains subjective visual quality.

Performance improvement on mobile devices using MVC+Prefetch Controller Pattern (MVC+Prefetch Controller 패턴을 사용한 모바일 기기의 성능향상 기법)

  • Im, Byung-Jai;Lee, Eun-Seok
    • The KIPS Transactions:PartD
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    • v.18D no.3
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    • pp.179-184
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    • 2011
  • Current mobile devices have surpassed its boundaries as a more communication tool to a smart device which provides additional features. These features have supported the smart life of its users, but have reached its limit from low-performance processors and short-battery time. These issues can be resolved b implementing higher performing hardware, but they come with a burden of high cost. This paper introduces a new way of managing computing resources in a mobile device by enhancing the quality of human-computer interaction. The real-speed felt by users are mainly influenced by the time it takes form a user's input to the device to display the completed result on the screen. Since the size of the screen for mobile devices are small, if the processor only fetch data to be used for displaying on screen, the time can be significantly reduced. MVC+Prefetch Controller pattern accomplished this goal by using the minimum amount of data from DB to fetch display and still manages to support high-speed data transfer to achieve seamless display. This idea has been realized by practice using Samsung mobile phone S8500, which demonstrated the superior performance on user's perspective.