• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.4
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• pp.165-172
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• 2023

Heterogeneous computing is a technology that utilizes different types of processors to perform parallel processing. It maximizes task processing and energy efficiency by leveraging various computing resources such as CPUs, GPUs, and FPGAs. On the other hand, edge computing has developed with IoT and 5G technologies. It is a distributed computing that utilizes computing resources close to clients, thereby offloading the central server. It has evolved to intelligent edge computing combined with artificial intelligence. Intelligent edge computing enables total data processing, such as context awareness, prediction, control, and simple processing for the data collected on the edge. If heterogeneous computing can be successfully applied in the edge, it is expected to maximize job processing efficiency while minimizing dependence on the central server. In this paper, experiments were conducted to verify the feasibility of various parallel programming models on high-end and low-end edge devices by using benchmark applications. We analyzed the performance of five parallel programming models on the Raspberry Pi 4 and Jetson Orin Nano as low-end and high-end devices, respectively. In the experiment, OpenACC showed the best performance on the low-end edge device and OpenSYCL on the high-end device due to the stability and optimization of system libraries.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.1-12
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• 2013

This paper explores design space of many-core processors for a fire feature extraction algorithm. This paper evaluates the impact of varying the number of cores and memory sizes for the many-core processor and identifies an optimal many-core processor in terms of performance, energy efficiency, and area efficiency. In this study, we utilized 90 samples with dimensions of $256{\times}256$ (60 samples containing fire and 30 samples containing non-fire) for experiments. Experimental results using six different many-core architectures (PEs=16, 64, 256, 1,024, 4,096, and 16,384) and the feature extraction algorithm of fire indicate that the highest area efficiency and energy efficiency are achieved at PEs=1,024 and 4,096, respectively, for all fire/non-fire containing movies. In addition, all the six many-core processors satisfy the real-time requirement of 30 frames-per-second (30 fps) for the algorithm.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.309-316
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• 2008

The mission-critical engagement control computer for air defense has to maintain its operation without any fault for a long mission time. The mission performed by large-scale and complex embedded software is extremely critical in terms of dependability and safety of computer system, and it is very important that engagement control computer has high reliability. The engagement control computer was implemented using four processors. The distributed computer composed of four processors quarantees the dependability and safety, and ASR fault-tolerant technique applied to each processor guarantees the reliability. In this paper, the mechanism and performance of ASR fault-tolerant technique are analysed. And MTBF, reliability, availability, and cost-effectiveness for ASR, DMR and TMR techniques applied to the engagement control computer are analysed. The mission-critical engagement control computer using software-based ASR fault-tolerant technique provides high reliability and fast recovery time at a low cost. The mission reliability of the engagement control computer using ASR technique in 4 processors board is almost same the reliability of the computer using TMR technique in 6 processors board. ASR technique is most suitable to the mission-critical engagement control computer.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.117-124
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro) TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.542-546
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• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.467-478
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• 2002

With the rapid development of wired or wireless Internet, various kinds of resource constrained mobile devices, such as cellular phone, PDA, homepad, smart phone, handhold PC, and so on, have been emerging into personal or commercial usages. Most software to be embedded into those devices has been forced to have the characteristic of flexibility rather than the fixedness which was an inherent property of embedded system. It means that recent technologies require the flexible embedding into the variety of resource constrained mobile devices. A document processor for XML which has been positioned as a standard mark-up language for information representation on the Web, is one of the essential software to be embedded into those devices for browsing the information. In this paper, a framework for configurable XML processor called EmXJ is designed and implemented for flexible embedding into various types of resource constrained mobile devices, and its advantages are compared to conventional XML processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1405-1411
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• 2022

Power management is still an important issue in embedded environments as hardware advances like high-performance processors. Power management methods such as DVFS control CPU frequencies in an adaptive manner for efficient power management in polling-based I/O programs such as network communication. This paper presents the problems of the existing power management method and proposes a new power management method. Through this, it is possible to reduce electric consumption by increasing the polling cycle in situations where the frequency of data reception is low, and on the contrary, in situations where data reception is frequent, it can operate at the maximum frequency without performance degradation. After implementing this as a code layer on the embedded board and observing it through Atmel's Power Debugger, the proposed method showed a performance improvement of up to 30% in energy consumption compared to the existing power management method.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1205-1210
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• 2004

The 4-20mA analog signal used in the various industrial fields to interface sensor in distributed process control has been replaced with relatively simple digital networks, called "fieldbus, and recently by Ethernet. Significant advances in Internet and computer technology have made it possible to develop an Internet based control, monitoring, and operation scheduling system for heating, ventilation and air-conditioning (HVAC) systems. The seamless integration of data networks with control networks allows access to any control point from anywhere. Field compatible field devices become so-called "smart" devices, capable of executing simple control, diagnostic and maintenance functions and providing bidirectional serial communication to higher level controller. The most important HVAC of BAS has received nationwide attention because of higher portion of more than 40% in building sector energy use and limited resources. This paper presents the Internet-based monitoring and control architecture and development of LonWorks control modules for AHU (air handling units) of HVAC in viewpoint of configuring BAS network. This article addresses issues in architecture section, electronics, embedded processors and software, and internet technologies.

• Journal of Mechanical Science and Technology
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• v.17 no.10
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• pp.1399-1410
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• 2003

In this paper, we develop a joystick manual driving algorithm for an electric vehicle called Cycab. Cycab is developed as a public transportation vehicle, which can be driven either by a manual joystick or an automated driving mode. The vehicle uses six motors for driving four wheels, and front/rear steerings. Cycab utilizes one industrial PC with a real time Linux kernel and four Motorola MPC555 micro controllers, and a CAN network for the communication among the five processors. The developed algorithm consists of two automatic vehicle speed control algorithms for normal and emergency situations that override the driver's joystick command and an open loop torque distribution algorithm for the traction motors. In this study, the algorithm is developed using SynDEx, which is a system level CAD software dedicated to rapid prototyping and optimizing the implementation of real-time embedded applications on distributed architectures. The experimental results verify the usefulness of the two automatic vehicle control algorithms.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.175-183
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• 2016

This paper brings out a novel method for reducing Near end and Far end Crosstalk using Electromagnetic Band Gap structures (EBG) in High Speed RF transmission lines. This work becomes useful in high speed closely spaced Printed Circuit Board (PCB) traces connected to multi core processors. By using this method, reduction of −40dB in Near-End Crosstalk (NEXT) and −60 dB in Far End Crosstalk (FEXT) is achieved. The results are validated through experimental measurements. Time domain analysis is performed to validate the signal integrity property of coupled transmission lines.