• Journal of Digital Convergence
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• v.13 no.11
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• pp.141-148
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• 2015

In this paper, for developing and implementing the HLS(Http Live Streaming) transmitter based embedded linux which is operated easily and cheap and lower power, portable in all networks and client environments compared to exist video live streaming transmitters. We design the developed HLS transmitter hardware using the Arm11 core and then porting the Embedded Linux OS(Operating System) and implementing the HLS protocol using the open source FFmpeg and Segmenter. For proving the performance of developed HLS transmitter, we make the testing environment for testing the performance of HLS transmitter including the notebook, iPhone, android Phone, Notebook and then analysis the received video in the client displayer. In this paper, we suggest the developed HLS transmitter performance data values higher than the Apple company's HLS recommended specification values and the picture of developed HLS transmitter operation in the testing environment. The application field of this paper result is that the man who works in the emergency situation take HLS and transmit the live emergency situation to the head quarter using this portable HLS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.140-150
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• 2006

In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.397-403
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• 2015

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.23-28
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• 2009

Testing of analog(and mixed-signal) circuits has been a difficult task for test engineers and effective test techniques to solve these problems are required. This paper develops a new technique which increases fault detection and diagnosis rates for analog circuits by using extended MTSS (Modified Time Slot Specification) technique based on MTSS proposed by the author. High performance current sensors with digital outputs are used as core components for these techniques. A fault diagnosis structure with minimal hardware overhead in ATE is also described.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.54-64
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• 2002

Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.

• The Journal of Advanced Prosthodontics
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• v.3 no.2
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• pp.90-95
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• 2011

PURPOSE. To compare the fracture resistance and the mode of failure of endodontically treated teeth restored with different post-core systems. MATERIALS AND METHODS. Root canal treatment was performed on 40 maxillary incisors and the samples were divided into four groups of 10 each. For three experimental groups post space preparation was done and teeth were restored with cast post-core (Group B), stainless steel post with composite core (Group C) and glass fiber post with composite core using adhesive resin cement (Group D). Control group (A) samples were selected with intact coronal structure. All the samples were prepared for ideal abutment preparation. All the samples were subjected to a load of 0.5 mm/min at $130^{circ}$.until fracture occurred using the universal testing machine. The fracture resistance was measured and the data were analyzed statistically. The fracture above the embedded resin was considered to be favorable and the fracture below the level was considered as unfavorable. The statistical analysis of fracture resistance between different groups was carried out with t-test. For the mode of failure the statistical analysis was carried out by Kruskal-Wallis test and Chi-Square test. RESULTS. For experimental group Vs control group the fracture resistance values showed significant differences (P<.05). For the mode of failure the chi-square value is 16.1610, which means highly significant (P=.0009) statistically. CONCLUSION. Endodontically treated teeth without post core system showed the least fracture resistance demonstrating the need to reinforce the tooth. Stainless steel post with composite core showed the highest fracture resistance among all the experimental groups. Teeth restored with the Glass fiber post showed the most favorable fractures making them more amenable to the re-treatment.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Steel and Composite Structures
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• v.1 no.3
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• pp.329-340
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• 2001

Cyclic response of "shear" connections between steel outrigger beams and reinforced concrete core walls is presented in this paper. The connections investigated in this paper consisted of a shear tab welded onto a plate that was connected to the core walls through multiple headed studs. The experimental data from six specimens point to a capacity larger than the design value. However, the mode of failure was through pullout of the embedded plate, or fracture of the weld between the studs and plate. Such brittle modes of failure need to be avoided through proper design. A capacity design method based on dissipating the input energy through yielding and fracture of the shear tab was developed. This approach requires a good understanding of the expected capacity of headed studs under combined gravity shear and cyclic axial load (tension and compression). A model was developed and verified against test results from six specimens. A specimen designed based on the proposed design methodology performed very well, and the connection did not fail until shear tab fractured after extensive yielding. The proposed design method is recommended for design of outrigger beam-wall connections.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2625-2627
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• 2004

Recently many technology of the T.T.P.(Train Tilting Processor) has been introduced for an efficient real-time operating system. but the problems of testing increasing complex digital integrated system continue to challenge the design and test community. Design main processor part that can be used on railroad synthesis control part by ARM CORE chip.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.123-128
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• 2004

Recent advancement in RF technology and wireless communications has enabled the development of noble networks. Bluetooth that can be used in various application field is a kind of WPAN(Wireless Personal Area Network) standard that is widely known. Bluetooth enables voice and data applications to operate simultaneously. Various applications have been implemented based on standard Profiles. In this paper, we describes the development of Biuetooth network AP(Access Point) system for network connection of Bluetooth devices. Unlike headset, mouse, and keyboard, the access point should have capability to support multiple connection and stabilized network throughput. We have designed and developed the hardware system, core stack and profiles on embedded system to comply with standard specification. Our system showed compatibility and good protocol performance through testing with lots of products that is available in market.