• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.232-233
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• 2007

We manufactured Liquid Crystal Polymer (LCP) and (1-x)CaTiO3-xLaAlO3 (CT-LA) ceramic composites and investigated dielectric properties to use as embedded capacitor in printed circuit boards and replace LTCC substrate. The dielectric properties of these composites are varied with volume fraction of CT-LA and ratios of CT/LA. Dielectric constants are in the range of 3~15. In addition, we could get low TCC and High Q value that could not achieve in other ceramic-polymer composites. Especially, in composite with x=0.01 and 30 vol% CT-LA, the dieletric constant and Q-value are 10 and 200, respectively. And more TCC is $-28{\sim}300ppm/^{\circ}C$ in the temperature range of $-55{\sim}125^{\circ}C$. We think that this composites can be used high-Q substrate material like LTCC and embedded temperature compensation capacitor in printed circuit boards.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.342-347
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• 2007

$Bi_6Mg_2Nb_4O_{21}(BMN)$ thin films were deposited at various substrates by sputtering system for embedded capacitor applications. BMN thin films deposited at room temperature are manufactured as MIM(Metal/Insulator/Metal) structures. Dielectric properties and leakage current density were investigated as a function of various substrates and thickness of BMN thin films. Leakage current density of BMN thin films deposited on CCL(Copper Clad Laminates) showed relatively high value ($1{\times}10^{-3}A/cm^2$) at an applied field of 300 kV/cm on substrates, possibly due to relatively high value of roughness(rms $50{\AA}$) of CCL substrates. 100 nm-thick BMN thin films deposited on Cu/Ti/Si substrates showed the capacitance density of $300 nF/cm^2$, a dielectric constant of 32, a dielectric loss of 2 % at 100 kHz and the leakage current density of $1{\times}10^{-6}A/cm^2$ at an applied field of 300 kV/cm. BMN capacitors are expected to be promising candidates as embedded capacitors for printed circuit board(PCB).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.150-152
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• 2004

The number of layers in rigid PCB(printed circuit board) is restricted, so the number of components can be embedded in module is restricted also. But using flexible multilayer PCB, the layers over than 7 can be evaluated. In this study, to verify the possibility of application of flexible multilayer PCB to RF modules, multilayered embedded capacitor is fabricated and analyzed. The characteristics of embedded capacitor is analyzed and compared to that of MLCC and LTCC capacitor. Embedded capacitor has better electrical features than MLCC and compatible one to LTCC capacitor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.343-351
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• 2008

In this paper, a spiral shaped common mode filter(CMF) embedded in a flexible printed circuit board(FPCB) is proposed for a multi-function cable. The CMF embedded in a FPC cable presents a new concept as a multi-function cable by the common mode rejection characteristics without a surface mounted device(SMD) CMF. The embedded CMF has a wideband common mode rejection bandwidth and an enhanced differential mode characteristics compared to conventional CMFs that use a magnetic material such as a ferrite of high loss. The proposed CMF of 3 turn inductors has a common mode rejection bandwidth from 0.4 GHz to 3.12 GHz and has 1.95 dB at 3 GHz, 6.97 dB at 8 GHz improvements of a differential mode insertion loss compared to the commercial LTCC(Low Temperature Co-fire Ceramics) CMFs.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1149-1152
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• 2003

Now a days, many different kinds of display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), and Liquid Crystal On Silicon (LCOS) are designed. And these display technologies will be used in many application products like High Definition Televisions (HDTVs) or mobile devices. In this paper, pattern generation circuit for display test is proposed. The proposed circuit will be embedded in the control circuit of display chip. Two differenct kinds of patterns is generated by the circuit. One is block pattern for color test, and the other is line pattern for pixel test. The shape of test pattern is determined by the values of registers in pattern generation circuit. The circuit is designed using Verilog HDL RTL code.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.201-204
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• 2007

In this paper, fully embedded and miniaturized diplexer device has been developed and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into a low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23 dB at 824-894 MHz and -0.7 and -22 dB at 1850-1990 MHz, respectively. Its size is $3.9mm{\times}3.9mm{\times}0.77mm$. The fabricated diplexer is the smallest one which is fully embedded into a low cost organic package substrate.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1366-1367
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• 2006

Embedded capacitor technology is one of the effective packaging technologies for further miniaturization and higher performance of electric package systems. So we used the 3D EM simulator for embedded capacitor design in 8-layed PCB(Printed Circuit Board). The designed capacitors value are 2 pF, 5pF, 10 pF, respectly. we investigated characteristics of capacitance - frequency and SRF(Self Resonance Frequency) as changing the rate of hight and width of upper pad of embedded capacitors.