• KSII Transactions on Internet and Information Systems (TIIS)
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• 제5권9호
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• pp.1528-1543
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• 2011

With increasing the using of wireless technologies in essential fields such as the medical application, this paper proposes different scenarios for the transmission of images over wireless networks. The paper uses the IEEE ZigBee 802.15.4 for applying the proposed schemes. It is a Wireless Personal Area Network (WPAN). This paper presents a novel chaotic interleaving scheme against error bursts. Also, the paper studies the proposed interleaver with the convolutional code with different constraint lengths (K). A comparison study between the standard scheme and proposed schemes for image transmission over a correlated fading channel is presented. The simulation results show the superiority of the proposed chaotic interleaving scheme over the traditional schemes. Also, the chaotic interleaver packet-by-packet basis gives a high quality image with (K=3) and reduces the need for the complex encoder with K=7.

• 센서학회지
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• 제32권4호
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• pp.219-222
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• 2023

Partial discharges (PD) have long been recognized as a major contributing factor to catastrophic failures in high-power equipment. As the demand for high voltage direct current (HVDC) facilities continues to rise, the significance of on-line and real-time monitoring of PD becomes increasingly prominent. In this study, we have designed, fabricated, and characterized a highly sensitive and cost-effective PD sensor comprising a pair of copper electrodes with different arc lengths. The key advantage of our sensor is its non-invasive nature, as it can be installed at any location along the entire power cable without requiring structural modifications. In contrast, conventional PD sensors are typically limited to installation at cable terminals or insulation joint boxes, often necessitating invasive alterations. Our PD sensor demonstrates exceptional accuracy in estimating PD location, with a success rate exceeding 95% in the straight sections of the power cable and surpassing 89% in curved sections. These remarkable characteristics indicate its high potential for realtime and on-line detection of PD.

• 전기학회논문지
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• 제59권4호
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• pp.693-699
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• 2010

General transformer's life is known as paper insulation' life. If a transformer is degraded by these aging factors, it is known that electrical, mechanical and chemical characteristics for transformer's oil-paper are changed. When the kraft paper is aged, the cellulose polymer chains break down into shorter lengths. It causes decrease in both tensile strength and degree of polymerization of paper insulation. The paper breakdown is accompanied by an increase in the content of furanic compounds within the dielectric liquid. In this paper it is aimed at analysis on correlation between aging characteristics for insulating diagnosis of thermally aged paper. For investigating the accelerated aging process of oil-paper samples accelerating aging cell was manufactured for estimating variation of paper insulation during 500 hours at $140^{\circ}C$ temperature. To derive the results, it was performed analysis such as tensile strength(TS), depolymerization(DP), dielectric strength(DS), relative permittivity, water content(WC) and furan compound(FC) for aged paper. Also for analyzing correlation between insulating degradation characteristics, we used linear regression method. As as results of linear regression analysis, there was a close correlation between TS and DP. WC, FC. But dielectric strength was a weak correlation with aging time.

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제5B권1호
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• pp.43-49
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• 2005

The high rate of voltage rise (dv/dt) in motor terminals caused by high-frequency switching and impedance mismatches between inverter and motor are known as the primary causes of irregular voltage distributions and insulation breakdowns on stator windings in IGBT PWM inverter-driven induction motors. In this paper, voltage distributions in the stator windings of an induction motor driven by an IGBT PWM inverter are studied. To analyze the irregular voltages of stator windings, high frequency parameters are derived from the finite element (FE) analysis of stator slots. An equivalent circuit composed of distributed capacitances, inductance, and resistance is derived from these parameters. This equivalent circuit is then used for simulation in order to predict the voltage distributions among the turns and coils. The effects of various rising times in motor terminal voltages and cable lengths on the stator voltage distribution are also presented. For a comparison with simulations, an induction motor with taps in the stator turns was made and driven by a variable-rising time switching surge generator. The test results are shown.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집(한일합동학술편); 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.857-862
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• 1987

Given a network with k specified vertices bi called centers, a cardinality constrained cover is a family {Bi} of k subsets covering the vertex set of a network, such that each subset Bi corresponds to and contains center bi, and satisfies a given cardinality constraint. A set of cardinality constrained overlapping territories is a cardinality constrained cover such that the total sum of T(B$_{i}$) for all subsets is minimum among all cardinality constrained covers, where T(B$_{i}$) is the summation of the shortest path lengths from center bi to every vertex in B$_{I}$. This paper considers a problem of finding a set of cardinality constrained overlapping territories. and proposes an algorithm for the Problem which has the time and space complexities are O(k$^{3}$$\mid$V$\mid$$^{2}$) and O(k$\mid$V$\mid$+$\mid$E$\mid$), respectively, where V and E are the sets of vertices and edges of a given network, respectively. The concept of overlapping territories has a possibility to be applied to a job assignment problem.oblem.

• 전기학회논문지
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• 제59권5호
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• pp.912-917
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• 2010

It was known that oil-filled transformer's life depended on insulating paper which was applied to transformers for insulating of transformer. Therefore when paper was aged, its electrical, mechanical and chemical characteristics were changed. Especially if operating temperature was high, paper was quickly damaged. As cellulose paper which was mainly used for solid insulation of transformers was degraded, the cellulose polymer chains broke down into shorter lengths and gases such as CO, $CO_2$, $CH_4$, $C_2H_4$ and so on were produced from paper. Also by-product known as furan compounds were producted from paper and it were dissolved within insulating oil. In this paper accelerating aging cell was aged during 60 hours at 100, 150, 180 and $200^{\circ}C$, respectively, so evaluating the chemical characteristics of cellulose paper by thermal. An it were performed analysis such as tensile strength(TS), dissolved gas analysis(DGA) and high performance liquid chromatography(HPLC). Also for analyzing of correlation between insulating degradation characteristics, it was performed linear regression method as statistical treatment.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.497-499
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• 2013

본 논문에서는 단락형 스터브에 의해 구현되는 이중 모드 공진기의 전달 함수를 수식적으로 해석하여 임의의 공진 주파수를 만족하는 이중 모드 공진기의 전송 선로와 스터브의 전기적 길이 및 임피던스를 계산하였다. 계산된 결과에 의하면 전송 선로의 전기적 길이는 공진 주파수에 의해 결정되며, 스터브의 전기적 길이는 공진 주파수 및 선로와 스터브의 임피던스에 의해 결정된다. 또한, 이중 모드 공진기를 이용하여 필터를 설계하기 위해 필터의 리플 값에 따른 인버터의 크기를 계산하였다. 계산된 결과에 의해 스터브의 임피던스에 따른 인버터의 변화는 거의 없으며 전송 선로의 임피던스가 작을수록 인버터의 크기는 증가하고 필터의 대역폭이 클수록 인버터의 크기가 증가함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.