• 전자공학회논문지 IE
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• v.48 no.4
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• pp.13-18
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• 2011

In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

• Journal of Adhesion and Interface
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• v.21 no.3
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• pp.86-92
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• 2020

We confirmed the effects on the device performances and the charge injection characteristics of organic field-effect transistor (OFET) by selectively differently controlling the surface energies on the contact region of the substrate where the source/drain electrodes are located and the channel region between the two electrodes. When the surface energies of the channel and contact regions were kept low and increased, respectively, the field-effect mobility of the OFET devices was 0.063 ㎠/V·s, the contact resistance was 132.2 kΩ·cm, and the subthreshold swing was 0.6 V/dec. They are the results of twice and 30 times improvements compared to the pristine FET device, respectively. As the results of analyzing the interfacial trap density according to the channel length, a major reason of the improved device performances could be anticipated that the pi-pi overlapping direction of polymer semiconductor molecules and the charge injection pathway from electrode is coincided by selective surface treatment in the contact region, which finally induces the decreases of the charge trap density in the polymer semiconducting film. The selective surface treatment method for the contact region between the electrode and the polymer semiconductor used in this study has the potential to maximize the electrical performances of organic electronics by being utilized with various existing processes to lower the interface resistance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.21-28
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• 2007

In this paper, in order to derive the two-dimensional field effect of n-InAlAs/InGaAs HEMTs, we suggested analytical model by solving the two-dimensional Poisson's equation in both InAlAs and InGaAs regions by taking into account the longitudinal field variation, field-dependent mobility, and the continuity condition of the channel current flowing within the quantum well shaped channel. Derived expressions for long and short channel devices would be applicable to the entire operating regions in a unified manner. Simulation results show that the drain saturation current increases and the threshold voltage decreases as drain voltage increases. Compared with the conventional model, the present model may offer more reasonable explanation for the drain-induced threshold voltage roll-off, the Early effect, and the channel length modulation effect. Furthermore, it is expected that the proposed model would provide more reasonable theoretical basis for analyzing various long and short channel InAlAs/InGaAs HEMT devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.869-875
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• 2017

Using TCAD simulation, performances of tunnel field-effect transistors (TFETs) was investigated. Drain current-gate voltage types of TFET structure such as single-gate TFET (SG-TFET), double-gate TFET (DG-TFET), L-shaped TFET (L-TFET), and Pocket-TFET (P-TFET) are simulated, and then as dielectric constant of gate oxide and channel length are varied their subthreshold swing (SS) and on-current ($I_{on}$) are compared. On-currents and subthreshold swings of the L-TFET and P-TFET structures with high electric constant and line tunneling were 10 times and 20 mV/dec more than those of the SG-TFET and DG-TFET using point tunneling, respectively. Especially, it is shown that hump effect which dominant current element changes from point tunneling to line tunneling, is disappeared in P-TFET with high-k gate oxide such as $HfO_2$. The analysis of 4 types of TFET structure provides guidelines for the design of new types of TFET structure which concentrate on line tunneling by minimizing point tunneling.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.2
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• pp.372-377
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• 2016

Communication flow is changing rapidly. Recently, a range of wearable devices such as wearable glasses and wearable watch, have been launched. These kinds of wearable devices help people to live a more comfortable life. Wearable devices most have an antenna for wireless communication. This paper reports a transparent antenna that is made of an optically transparent material for wearable glasses. Transparent antenna can be applied to smart windows and will not disturb the view of user. IZTO/Ag/IZTO multilayer electrode has higher electrical and optical properties. This antenna is available because of its good electrical properties. This study measured the performance of the proposed transparent antenna, which is made of a multilayer electrode, applied to a lens. The proposed antenna was simulated with several substrates. The antenna impedance was matched with length and width of the antenna. The antenna's conductivity and transparency was measured using a HMS-3000 and UV-spectrometer. A 40nm thick Ag single layer antenna was fabricated on a flexible polyimide substrate for comparing the antenna performances. The fabricated antenna is useable at a frequency of 2.4-2.5GHz, which is suitable for Wifi communications and has peak gain of 2.89dBi and an efficiency of 34%.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of Sensor Science and Technology
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• v.11 no.2
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• pp.102-110
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• 2002

The chemical and mechanical characteristics of a new surface modifier, dichlorodimethysilane (DDMS, $(CH_3)_3SiCl_2$), for stiction-free polysilicon surfaces are reported. The main strategy is to replace the conventional monoalkyltrichlorosilane(MTS, $RSiCl_3$) such as octadecyltrichlorosilane (ODTS) or 1H,1H,2H,2H-perfluorodecyltrichlorosilane (FDTS) with dialkyldichlorosilane (DDS, $R_2SiCl_2$) with twit short chains, especially DDMS. DDMS, with shorter chains in aprotic media, rapidly deposits on the chemically oxidized polysilicon surface at room temperature and successfully prevents long cantilevers of 3 mm in length from in-use as well as release stiction. DDMS-modified polysilicon surfaces exhibit satisfactory hydrophobicity, long term stability and thermal stability, which are comparable to those of FDTS. DDMS as an alternative to FDTS and ODTS provides a few valuable advantages; ease in handling and long-term storage in solution, low temperature-dependence and low cost. In addition to the new modifier molecule, the simplified process of direct release right after washing the modified surface with isooctane was proposed to cut the processing time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.151-157
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• 2007

We have presented a compact two-wire helical antenna adopted an open stub in opposite to a feeding point, which is for a T-DMB antenna of mobile devices. By adjusting the length of the open stub or pasting a dielectric material on the open stub, the input impedance around 200 MHz, bands of the T-DMB, can be easily control, even though the total height of the antenna is less than 8 cm(0.053 $\lambda$ at 200 MHz). The operating mechanism of the antenna is explained by using equivalent circuits of two modes, an unbalanced mode and a balanced mode. Based on the analysis of the equivalent circuits, the effects of using the open stub are validated. Several proposed antennas have been fabricated and measured. One of the fabricated antennas has -10 dB impedance bandwidth of $196{\sim}204$ MHz(8 MHz) whose value covers one channel of the T-DMB(6 MHz). The measured $S_{21}$ of the antenna is -38.6 dB which is about 17 dB higher than that of a monopole antenna whose height is same with the proposed antenna.

• Korean Journal of Optics and Photonics
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• v.25 no.3
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• pp.131-136
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• 2014

In this paper we have implemented a temperature-insensitive polarimetric fiber strain sensor based on a Sagnac birefringence interferometer composed of a short polarization-maintaining photonic crystal fiber (PM-PCF), a 3-dB fiber coupler, and polarization controllers. The PM-PCF used as a sensor head was 2 cm long, which is the shortest length for a sensing element compared to other polarimetric fiber strain sensors using a PM-PCF. The proposed sensor showed a strain sensitivity of ${\sim}0.87pm/{\mu}{\varepsilon}$ with a strain measurement range from 0 to $8m{\varepsilon}$. The temperature sensitivity was also investigated and measured as approximately $-12pm/^{\circ}C$, when ambient temperature changed from 30 to $100^{\circ}C$. This temperature sensitivity is about 82 times smaller than that of conventional polarization-maintaining fiber (approximately $-990pm/^{\circ}C$). In particular, from a practical perspective we have experimentally and theoretically confirmed that the wavelength selected for the indicator dip location does not make a significant difference in the strain sensitivity.