• Journal of Korea Port Economic Association
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• v.36 no.1
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• pp.41-58
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• 2020

This study aims to investigate the technical efficiency of major container ports in the Bay of Bengal area and to study how certain factors influence the efficiency of container ports and terminals. The research is conducted on the four main container ports in the Bay of Bengal area, namely, Colombo Port in Sri Lanka, Chennai Port in India, Chittagong Port in Bangladesh, and Yangon Port in Myanmar. There are three input variables (quay length, storage area, and the number of cranes) and two output variables (throughput twenty-foot equivalent units and vessel calls) chosen for the process in this study. This paper evaluates the efficiency score of the defined variables and suggests implications for further improvement of the core competitiveness of the four selected ports. The findings indicate that Colombo Port is the most efficient on a technical scale, followed by Chennai Port, Yangon Port, and Chittagong Port. However, the slack and radial movement calculation results show that the inputs and outputs of the four ports need to be adjusted to be efficient and to reduce the amount of resources that are wasted. The results validate the adaptability of the improved data envelopment analysis algorithm in port efficiency analysis. The research findings provide an overview of the efficiencies of the selected container ports and can potentially affect the port management decisions made by policymakers, terminal operators, and carriers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of Internet Computing and Services
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• v.5 no.1
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• pp.67-84
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• 2004

Real-time database systems (RTDBS) are database systems whose transactions are associated with timing constraints such as deadlines. Therefore transaction needs to be completed by a certain deadline. Besides meeting timing constraints, a RTDBS needs to observe data consistency constraints as well. That is to say, unlike a conventional database system, whose main objective is to provide fast average response time, RTDBS may be evaluated based on how often transactions miss their deadline, the average lateness or tardiness of late transactions, the cost incurred in transactions missing their deadlines. Therefore, in RTDBS, transactions should be scheduled according to their criticalness and tightness of their deadlines, even If this means sacrificing fairness and system throughput, And It always must guarantee preceding process of the transaction with the higher priority. In this paper, we propose an efficient real-time scheduling algorithm (Multi-level EFDF) that alleviates problems of the existing real-time scheduling algorithms, a real-time concurrency control algorithm(2PL-FT) for firm and soft real-time transactions. And we compare the proposed 2PL F[ with AVCC in terms of the restarting ratio and the deadline missing ratio of transactions. We show through experiments that our algorithms achieve good performance over the other existing methods proposed earlier.

• Weed & Turfgrass Science
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• v.4 no.4
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• pp.308-314
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• 2015

This study was conducted to establish a fluorescence assay system for high efficient mass screening of the herbicides causing rapid membrane peroxidation, based on the fact that peroxide in cellular leakage could be fluorometrically determined through the fuorescent compounds formed after reacting with homovanillic acid (HVA) and peroxidase (HRP). The assay procesure established in this study was as follows. Only single disc (4 mm diameter) excised from cucumber cotyledon is placed on the well containing test solution ($200{\mu}L$) with 96-well microplate. The plate is shaking-incubated for 8 h under light condition. Then after removing the cucumber disc, HVA and HRP are supplied in the medium buffer and incubated for 5 min at room temperature. Fluorescence values are determined at Ex 320 nm/Ex 425 nm. The higher fluorescence values are obtained in the treatment of chemical having higher herbicidal activity. Using this assay with 96-well microplates, a large number of herbicides inducing rapid membrane peroxidation seemed to be screened more efficiently than spectrophotometric microtiter assay reported previously.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of Navigation and Port Research
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• v.38 no.4
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• pp.349-356
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• 2014

In the underwater communication, the performance of system is reduced because of the inter-symbol interference occur by the multi-path. In the recent years, to deal with poor channel environment and improve the throughput, the efficient concatenated structure of equalization, channel codes and Space Time Codes has been studied as MIMO system in the underwater communication. Space Time Codes include Space Time Block Codes and Space Time Trellis Codes in underwater communication. Space Time Trellis Codes are optimum for equalization and channel codes among the Space Time Codes to apply in the MIMO environment. Therefore, in this paper, turbo pi codes are used for the outer code to efficiently transmit in the multi-path channel environment. The inner codes consist of Space Time Trellis Codes with transmission diversity and coding gain in the MIMO system. And Zero Forcing method is used to remove inter-symbol interference. Finally, the performance of this model is simulated in the underwater channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.65 no.4
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• pp.496-507
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• 2020

Virus infections of apples result in lowered commercial qualities such as low sugar content, weakened tree vigor, and malformed fruits. An effective way to control viruses is to produce virus-free plants based on the development of an accurate and sensitive diagnostic method. In this study, real-time PCR assays based on SYBR Green I and TaqMan probes were developed for detecting ASGV, ASPV, and ApMV viruses. These methods can detect and quantify 10³ to 10¹¹ RNA copies/μL of each virus separately. Compared with methods with two different dyes, the SYBR Green I-based method was efficient for virus detection as well as for assay using the TaqMan probe. Field tests demonstrated that real-time PCR methods developed in this study were applicable to high-throughput diagnoses for virus research and plant quarantine.

• The KIPS Transactions:PartC
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• v.14C no.4
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• pp.349-358
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• 2007

Ethernet Passive Optical Network(EPON), which is one of PON technologies for realizing FTTx(Fiber-To-The-Curb/Home/Office), can cost-effectively construct optical access networks. In addition, EPON can provide high transmission rate up to 10Gbps and it is compatible with existing customer devices equipped with Ethernet card. To effectively control frame transmission from ONUs to OLT EPON can use Multi-Point Control Protocol(MPCP) with additional control functions in addition to Media Access Control(MAC) protocol function. For EPON, many researches on intra- and inter-ONU scheduling algorithms have been performed. Among the inter-ONU scheduling algorithms, IPS(Interleaved Polling with Stop) based on polling scheme is efficient because OLT assigns available time portion to each ONU given the request information from all ONUs. Since the IPS needs an idle time period on uplink between two consecutive frame transmission periods, it wastes time without frame transmissions. In this paper, we propose a dynamic bandwidth allocation algorithm to increase the channel utilization on uplink and evaluate its performance using simulations. The simulation results show that the proposed Two-phase Cycle Danamic Bandwidth Allocation(TCDBA) algorithm improves the throughput about 15%, compared with the IPS and Fast Gate Dynamic Bandwidth Allocation(FGDBA). Also, the average transmission time of the proposed algorithm is lower than those of other schemes.