• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.297-300
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• 2000

This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by “Radix-4/2”, uses the feature of existing radix-2$^3$algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 campared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2$^3$algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2$^3$algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.209-213
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• 2007

In this paper, we propose more efficient implementation architecture for realizing combination of heterogeneous routing protocols in wireless mesh routes. For realizing heterogeneous routing protocol in wireless mesh router, the following should be considered; which position in OS platform protocols should be implemented, how to define the common API for multiple routing protocols, how to provide architecture for providing high data transfer throughput and for supporting multi platform, and finally how to verify the throughput of protocol by using simulator. For solving those consideration, we propose HRPC(Heterogeneous Routing Protocol Coordinator) and describe the method for testing the protocols.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6A
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• pp.494-499
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• 2009

In this paper, we provide an efficient method of user selection for achieving the maximum system throughput in downlink multiuser Multiple-Input Multiple-Output (MIMO) systems. A proposed method is for selecting a fine user set only with powers of each user channel and angles between them. This algorithm is simpler than SUS because there is no considering about the optimal value of correlation. The proposed method finds the user set toward maximizing system throughput, so it has high performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.702-709
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• 2003

In this paper, we propose an efficient and QoS-aware MAC scheduling algorithm for Bluetooth, which considers both throughput and delay performance of each Master-Slave pair in scheduling decisions, and thus, attempts to maximize overall performance. The proposed algorithm, MTDPP (Modified Throughput-Delay Priority Policy), makes up for the drawbacks of T-D PP (Throughput-Delay Priority Policy) proposed in [6] and improves the performance. Since Bluetooth employs a master-driven TDD based scheduling algorithm, which is basically operated with the Round Robin policy, many slots may be wasted by POLL or NULL packets when there is no data waiting for transmission in queues. To overcome this link wastage problem, several algorithms have been proposed. Among them, queue state-based priority policy and low power mode-based algorithm can perform with high throughput and reasonable fairness. However, their performances may depend on traffic characteristics, i.e., static or dynamic, and they require additional computational and signaling overheads. In order to tackle such problems, we propose a new scheduling algorithm. Performance of our proposed algorithm is evaluated with respect to throughput and delay. Simulation results show that overall performances can be improved by selecting suitable parameters of our algorithm.

• The Transactions of the Korea Information Processing Society
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• v.7 no.9
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• pp.2827-2835
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• 2000

In recent years, much attention has been focused on improving I/O devices' processing speed which is essential in such large data processing areas as multimedia data processing. And studies on high-performance parallel file systems are considered to be one of such efforts. In this paper, an efficient disk allocation scheme is proposed for high-performance parallel file systems. In other words, the concept of a parallel disk file's parallelism is defined using data declustering characteristic of a given parallel file. With the concept, an efficient disk allocation scheme is proposed which calculates the appropriate degree of data declustering on disks for each parallel file in order to obtain the maximum throughput when more than one parallel file is used at the same time. Since, calculation for obtaining the maximum throughput is too complex as the number of parallel files increases, an approximate disk allocation algorithm is also proposed in this paper. The approximate algorithm is very simple and especially provides very good results when I/O workload is high. In addition, it has shown that the approximate algorithm provides the optimal disk allocation for the maximum throughput when the arrival rate of I/O requests is infinite.

• Journal of Satellite, Information and Communications
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• v.3 no.1
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• pp.8-14
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• 2008

In this paper, we analyze throughput performance of MF-TDMA scheme and QS MC-DS/CDMA(quasi-synchronous MC-DS/CDMA) scheme based on scrambling on WH sequence and PPGC sequence in early frequency offset caused by high speed transfer terminal. QS MC-DS/CDMA scheme with scrambled WH sequence shows 5.7% higher throughput than MF-TDMA scheme and 8% higher throughput than QS MC-DS/CDMA with PPGC sequence in high speed transfer terminal environment such as maximum 1000Km/h speed with high frequency of Ka-band. Finally, we show that QS MC-DS/CDMA scheme with scrambled WH sequence is more efficient than traditional MF-TDMA scheme at the aspect of throughput in DVB-RCS system with Ka frequency band.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.750-759
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• 2012

This paper addresses the collision resolution issue to enhance the performance of wireless sensor networks based on IEEE 802.15.4 slotted CSMA/CA. Some solutions in existing work try to solve this issue by adjusting Backoff Exponent (BE) value or Backoff Period (BP). In contrast to the existing solutions, the proposed scheme in this paper aims at providing high system throughput, but also achieving efficient energy consumption of sensor nodes by using Preamble Address (PA). For this, in the proposed scheme, only one sensor node begins data packet transmission by performing PA contention phase with other nodes before sending each data packet. Our simulation results show that the proposed scheme outperforms existing algorithms in terms of energy consumption and throughput.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.306-309
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• 2005

We consider the multi-objective optimization of a multi-service arrayed-waveguide grating-based single-hop metro WDM network with the two conflicting objectives of maximizing throughput while minimizing delay. We develop and evaluate a genetic algorithm based methodology for finding the optimal throughput-delay tradeoff curve, the so-called Pareto-optimal frontier. Our methodology provides the network architecture and the Medium Access Control protocol parameters that achieve the Pareto-optima in a computationally efficient manner. The numerical results obtained with our methodology provide the Pareto-optimal network planning and operation solution for a wide range of traffic scenarios. The presented methodology is applicable to other networks with a similar throughput-delay tradeoff.